2010 International Conference on Field Programmable Logic and Applications 2010
DOI: 10.1109/fpl.2010.50
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A Reconfigurable Analog Processor Based on FPAA with Coarse-Grained, Heterogeneous Configurable Analog Blocks

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Cited by 2 publications
(2 citation statements)
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“…Based on the CMOS technology, the mixed PSoC integrated the 32-bit CPU, FPAA, ADC, DDC, DUC, DAC and other digital IP units, and realized the analog input signal processing, analog to digital conversion, the baseband digital signal processing and other functions on a chip. Considering the first stage of the capacitor mismatch errors, fuse trimming technology is adopted to make a 2-bit trimming [4] , behavioral simulation results after trimming depicts in figure 4: SFDR = 88dB, SNR = 73dB. The indicator meets design requires.…”
Section: Results Of Implement and Simulationmentioning
confidence: 99%
“…Based on the CMOS technology, the mixed PSoC integrated the 32-bit CPU, FPAA, ADC, DDC, DUC, DAC and other digital IP units, and realized the analog input signal processing, analog to digital conversion, the baseband digital signal processing and other functions on a chip. Considering the first stage of the capacitor mismatch errors, fuse trimming technology is adopted to make a 2-bit trimming [4] , behavioral simulation results after trimming depicts in figure 4: SFDR = 88dB, SNR = 73dB. The indicator meets design requires.…”
Section: Results Of Implement and Simulationmentioning
confidence: 99%
“…A number of recent papers have been written regarding using reconfigurable analog circuits called Field Programmable Analog Arrays (FPAA) for low level control.This paper and [13] are based around custom FPAAs, but many are based on the switch-capacitor Anadigm IC design [14], [15], [16]. General references concerning PID controllers are [17], [18], [19], and [20].…”
Section: B Analog Controlmentioning
confidence: 99%