A Reconfigurable Built-In Self-Repair Scheme for Multiple Repairable RAMs in SOCs

Tseng, Tsu-Wei; Li, Jin-Fu; Hsu, Cheng-Hsin; Pao, A.; Chiu, Kevin Kuan‐Shun; Chen, E.

doi:10.1109/test.2006.297688

Cited by 22 publications

(8 citation statements)

References 18 publications

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“…It is inevitable to seek for efficient methodologiesfor repairing multiple memory cores. In [9]- [11], areconfigurable BISR scheme for repairing multiple RAMsis proposed. However, the traditional redundant mechanisms (SRs/SCs) are used.…”

Section: Fault Tolerant In Memorymentioning

confidence: 99%

Robust Fault Tolerance in Content Addressable Memory Interface

Kumar¹

2017

IOSR JVSP

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Section: Fault Tolerant In Memorymentioning

confidence: 99%

Robust Fault Tolerance in Content Addressable Memory Interface

Kumar¹

2017

IOSR JVSP

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“…PREVIOUS WORK Built In Self Repair (BISR) is becoming popular due to its higher test speed and dynamic reconfiguration capabilities [5] [8] [7][9] [10]. Memory BISR (MBISR) involves (i) testing the memory using MBIST to extract fault locations (ii) performing redundancy analysis to determine how to replace faulty cells with spare ones and (iii) setting up reconfiguration hardware used for re-mapping faulty addresses with functional spares.…”

Section: Introducitonmentioning

confidence: 99%

“…They use a reconfigurable built in redundancy analysis in addition to a BIST circuit in order to repair RAMs with various sizes and redundancy organizations. In [10] a BISR for multiple repairable RAM in an MPSoC is presented. As each of the cores can have different sizes or redundancy architectures, a built in redundancy analysis architecture is also proposed.…”

Section: Introducitonmentioning

confidence: 99%

A DFT Methodology for Repairing Embedded Memories of Large MPSoCs

Ganeshpure

Kundu

2012

2012 IEEE Computer Society Annual Symposium on VLSI

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Memory Built-In Self-Test (MBIST) is used to test large memories embedded in Multi-Processor System on Chip (MPSoC). With increase in memory size, memory repair becomes necessary to improve yield. Memory repair consists of complex offline analysis requiring (i) fault diagnosis and (ii) optimizing reconfiguration based on failure map and available spare resources. This paper presents an embedded repair scheme that uses resources within a MPSoC. The main challenge involves establishing integrity of such internal resources before they are used for repair. We propose a layered approach to testing that (i) tests local processor cache first and uses (ii) software based selftesting of limited processor functions using (iii) a small program loaded into a cache from tester, which then (iv) serves as a vehicle for memory repair. This repaired memory can store and run larger software-based self-test programs to test the remaining systems. Software simulation is used to demonstrate feasibility of the proposed DFT scheme and test methodology. The main advantages of this approach are (i) avoidance of memory testers that are typically necessary for memory repair, (ii) avoiding additional hardware to support repair by using existing resources and (iii) testing all components using a logic tester.

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“…This problem is detrimental to the yield of RAMs. Therefore, numerous approaches to solving this problem have been proposed in recent years (Youngs and Paramanandam 1997;Kim et al 1998;Jone, Huang, and Das 2003;Li, Yeh, Huang, and Wu 2005;Tseng et al 2006;Argyrides, Zarandi, and Pradhan 2007;Sun, Feng, and Zhang 2008). One of these methods is to use redundant elements to replace defective elements.…”

Section: Introductionmentioning

confidence: 99%

Optimal cutting design and analysis for fault-tolerant scheme of redundant memories

Huang

Chang

Fang

2010

International Journal of Systems Science

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Fault-tolerant design for memory production is beginning to play an important role in increasing the yield rate of manufacturing. To improve the reliability of memory manufacturing, there are many methods that have been proposed. One of the most used technologies is replacing the faulty cells with spare memory interleaved in the memory. Nowadays, laser-cutting technology improves the yield of memories because of the enhancement of the use of spare lines. However, the issue of choosing a cutting location significantly affects the utilisation of spare lines. A bad cutting location can even render it useless. To use spare lines more efficiently, this article proposes two algorithms. The first one is designed to seek out a good cutting location. It corrects some defects of previous algorithms and provides a better approach to finding cutting candidates. In addition, because most heuristic solution-finding algorithms do not work properly under the condition of cutting memory, the second algorithm, called modification of most-repair is proposed to help make the decision as to whether or not a solution exists for the faulty pattern. We can find an optimal solution by combing these two algorithms. The experimental results show that our proposed algorithms increase the reparable percentage of a 1024-by-1024 memory from 55 to 100% and also improve both the reliability of memory manufacturing and the flexibility of spare lines.

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A Reconfigurable Built-In Self-Repair Scheme for Multiple Repairable RAMs in SOCs

Cited by 22 publications

References 18 publications

Robust Fault Tolerance in Content Addressable Memory Interface

Robust Fault Tolerance in Content Addressable Memory Interface

A DFT Methodology for Repairing Embedded Memories of Large MPSoCs

Optimal cutting design and analysis for fault-tolerant scheme of redundant memories

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