A Reconfigurable Five-Stage Pipelined SAT Solver

Abstract

Several approaches have been proposed to accelerate the NP-complete Boolean Satisfiability problem (SAT) using reconfigurable computing. In this paper, we present a fivestage pipelined SAT solver. The first stage is a variable decider that, in the normal flow, assigns a free variable from a set of statically pre-ordered variables. In case of conflict, where one or more of the SAT CNF clauses is unsatisfied, the highest ordered variable from a pool of conflicting variables is reassigned or freed. The second stage fetches the effect of the current assigned variable on the SAT instance clauses from a memory pre-initialized with the effect of each variable on all clauses. This data is fed to the next stage, the clause evaluator. The fourth stage is the conflict detector that detects if there is a conflict and, if there is, it detects the index of the first unsatisfied clause. The last stage fetches the conflicting variables (variables in the unsatisfied clause) from a memory containing variables associated with each clause. Our approach's feasibility is evaluated through instances from the DIMACS benchmarks suite. Pipelining allows retaining same clock frequency of an equivalent non-pipelined implementation while achieving an average of three times speedup in performance.