Proceedings of the 2016 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE) 2016
DOI: 10.3850/9783981537079_0775
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A Reconfigurable Heterogeneous Multicore with a Homogeneous ISA

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Cited by 15 publications
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“…In DynamIQ, cores from different sizes can be mixed in the same cluster and share a coherent cache for fast thread migration, allowing for more diverse design space exploration. Nonetheless, there are many works employing different strategies to implement heterogeneous processors of single-ISA [21], from using DVFS to reach performance asymmetry in different voltage domains [22] to using binary translation to keep transparency between cores and accelerators [23].…”
Section: Related Workmentioning
confidence: 99%
“…In DynamIQ, cores from different sizes can be mixed in the same cluster and share a coherent cache for fast thread migration, allowing for more diverse design space exploration. Nonetheless, there are many works employing different strategies to implement heterogeneous processors of single-ISA [21], from using DVFS to reach performance asymmetry in different voltage domains [22] to using binary translation to keep transparency between cores and accelerators [23].…”
Section: Related Workmentioning
confidence: 99%