A Reconfigurable Implementation of the New Secure Hash Algorithm

Zeghid, Medien; Bouallègue, Belgacem; Baganne, Adel; Machhout, Mohsen; Tourki, Rached

doi:10.1109/ares.2007.17

Cited by 15 publications

(18 citation statements)

References 6 publications

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“…Our implementation makes the critical paths shorter than that of Chaves and removes five adders together with In comparison with commercial product as Helion [13], our work is much better in throughput and area performance terms, and achieves 30% better in throughput, although the area is only 2% bigger. Our area performance rate is 17% higher than Zeghid [4], although the throughput is 6% smaller due to the two steps unrolled architecture used by Zeghid. Since Aisopos [5] uses the hardware duplication technique, our hardware size is 73% smaller, and area performance rate is 39% better, but the throughput is 20% smaller.…”

Section: Comparison With Related Workmentioning

confidence: 90%

“…The reduction in number of steps helps these architectures to gain high throughput with low frequency. These architectures can be seen in Lien [2] with 5 steps unrolling, Zeghid [4] with two steps unrolling, and McEvoy [3] with two steps and 4 steps unrolling. Those unrolling architectures also often combine with the pipeline technique to increase the frequency.…”

Section: Unrolling Pipeline Architecturesmentioning

confidence: 99%

“…5 and Eqs. (4) show that all operations in each stage contain up to three adders, arranged into two adder-layers. Hence, this architecture achieves latency balance in all stages.…”

Section: Computation Postponement To Shorten Critical Path In New-a Cmentioning

confidence: 99%

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Pipelining a Multi-Mode SHA-384/512 Core with High Area Performance Rate

Hoang

Yamazaki

Oyanagi

2009

IEICE Trans. Inf. & Syst.

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SUMMARYThe security hash algorithm 512 (SHA-512), which is used to verify the integrity of a message, involves computational iterations on data. The huge computation delay generated in such iterations limits the entire throughput of the system and makes it difficult to pipeline the computation. We describe a way to pipeline the computation using finegrained pipelining with balanced critical paths. In this method, one critical path is broken into two stages by using data forwarding. The other critical path is broken into three stages by using computation postponement. The resulting critical paths all have two adder-layers with some data movements, and thus are balanced. In addition, the method also allows register reduction. Also, the similarity in SHA-384 and SHA-512 are used for a multi-mode design, which can generate a message digest for both versions with the same throughput, but with only a small increase in hardware size. Experimental results show that our implementation achieved not only the best area performance rate (throughput divided by area), but also a higher throughput than almost all related work.

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Section: Comparison With Related Workmentioning

confidence: 90%

Section: Unrolling Pipeline Architecturesmentioning

confidence: 99%

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Pipelining a Multi-Mode SHA-384/512 Core with High Area Performance Rate

Hoang

Yamazaki

Oyanagi

2009

IEICE Trans. Inf. & Syst.

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“…Reconfigurable architecture design is an interesting research topic of cryptosystem recently; among the existing reconfigurable designs, some focus on hash function, e.g., SHA-2 [12][13][14][15]; some focus on block cipher algorithm, e.g., AES [16,17]; some focus on public-key cryptography, e.g., elliptic curve cryptography [18,19]. Reconfigurable design can be configured for different mode up to the requirement of cryptosystem, provide different performance and flexibility, which is much more attractive than fixed architecture design.…”

Section: Fpga Implementationmentioning

confidence: 99%

RAM-Based Reconfigurable Implementation of the MD6 Hash Function

Gao

Wang

et al. 2009

2009 International Conference on Embedded Software and Systems

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Recent breakthroughs in cryptanalysis of standard hash functions like SHA-1 and MD5 raise the need for alternatives. The MD6 hash function is developed by a team led by Professor Ronald L. Rivest in response to the call for proposals for a SHA-3 cryptographic hash algorithm by the National Institute of Standards and Technology. The hardware performance evaluation of hash chip design mainly includes efficiency and flexibility. In this paper, a RAM-based reconfigurable FPGA implantation of the MD6-224/256/384 /512 hash function is presented. The design achieves a throughput ranges from 118 to 227 Mbps at the maximum frequency of 104MHz on low-cost Cyclone III device. The implementation of MD6 core functionality uses mainly embedded Block RAMs and small resources of logic elements in Altera FPGA, which satisfies the needs of most embedded applications, including wireless communication. The implementation results also show that the MD6 hash function has good reconfigurability.

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“…The Blue Midnight Wish hash function (BMW) is one of the fastest (in software) proposed new designs in the SHA-3 competition in software [4]. In this paper, low area FPGA and ASIC implementations for Blue Midnight Wish compression function with digest size of 256 bits (BMW-256) [5] and comparison with others [6] are introduced.…”

Section: Introductionmentioning

confidence: 99%

Low area FPGA and ASIC implementations of the hash function “Blue Midnight Wish-256”

El-Hadedy¹,

Gligoroski

Knapskog³

et al. 2009

2009 International Conference on Computer Engineering &Amp; Systems

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Hash functions are widely used in information security and cryptography. They are used in countless applications such as message authentication codes (MAC), Digital Signatures (DS) and mobile trusted modules (MTM). Serious attacks have been reported against cryptographic hash algorithms, including SHA-1. Because the SHA-1 and SHA-2 families share a similar design, the National Institute of Standards and Technology (NIST) in 2007 decided to start a world-wide development process for choosing the next secure hash standard SHA-3. A pivotal part of the process is an open competition for bringing forward new and secure cryptographic hash functions. The Blue Midnight Wish hash function is one of the second round candidates for the SHA-3 competition. In this paper, we describe low area FPGA and ASIC implementations for the Blue Midnight Wish compression function with digest size of 256 bits (BMW-256).Using Xilinx FPGA platform Virtex 5 "XC5VLX30", we implemented BMW-256 using 1986 slices (including the internal memory), and using only 122 slices for an implementation that uses external memory. By using 0.8 m CMOS standard cell library the ASIC implementation of BMW-256 takes approximately 13.5 Kgates (including the internal memory), and only 4 Kgates for an implementation that uses external memory.

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A Reconfigurable Implementation of the New Secure Hash Algorithm

Cited by 15 publications

References 6 publications

Pipelining a Multi-Mode SHA-384/512 Core with High Area Performance Rate

Pipelining a Multi-Mode SHA-384/512 Core with High Area Performance Rate

RAM-Based Reconfigurable Implementation of the MD6 Hash Function

Low area FPGA and ASIC implementations of the hash function “Blue Midnight Wish-256”

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A Reconfigurable Implementation of the New Secure Hash Algorithm

Cited by 15 publications

References 6 publications

Pipelining a Multi-Mode SHA-384/512 Core with High Area Performance Rate

Pipelining a Multi-Mode SHA-384/512 Core with High Area Performance Rate

RAM-Based Reconfigurable Implementation of the MD6 Hash Function

Low area FPGA and ASIC implementations of the hash function &#x201C;Blue Midnight Wish-256&#x201D;

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Low area FPGA and ASIC implementations of the hash function “Blue Midnight Wish-256”