A Reconfigurable In-SRAM Computing Architecture for DCNN Applications

Lin, Yu-Hsien; Liu, Chi; Hu, Chia-Lin; Chang, Kuang-Yi; Chen, Jia-Yin; Jou, Shyh-Jye

doi:10.1109/vlsi-dat52063.2021.9427349

Cited by 5 publications

(2 citation statements)

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“…The IMC macro used in this paper is based on the binary neural network macro from our previous work [17]. One IMC macro contains 8 64 × 64 banks as Fig.…”

Section: Design For Non-ideal Effects Of the Imc Macromentioning

confidence: 99%

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A 14 μJ/Decision Keyword-Spotting Accelerator With In-SRAMComputing and On-Chip Learning for Customization

Chiang

Chang

Jou

2022

IEEE Trans. VLSI Syst.

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Keyword spotting has gained popularity as a natural way to interact with consumer devices in recent years. However, because of its always-on nature and the variety of speech, it necessitates a low-power design as well as user customization. This paper describes a low-power, energy-efficient keyword spotting accelerator with SRAM based in-memory computing (IMC) and on-chip learning for user customization. However, IMC is constrained by macro size, limited precision, and nonideal effects. To address the issues mentioned above, this paper proposes bias compensation and fine-tuning using an IMC-aware model design. Furthermore, because learning with low-precision edge devices results in zero error and gradient values due to quantization, this paper proposes error scaling and small gradient accumulation to achieve the same accuracy as ideal model training. The simulation results show that with user customization, we can recover the accuracy loss from 51.08% to 89.76% with compensation and fine-tuning and further improve to 96.71% with customization. The chip implementation can successfully run the model with only 14uJ per decision. When compared to the state-of-the-art works, the presented design has higher energy efficiency with additional on-chip model customization capabilities for higher accuracy.

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“…The IMC macro used in this paper is based on the binary neural network macro from our previous work [17]. One IMC macro contains 8 64 × 64 banks as Fig.…”

Section: Design For Non-ideal Effects Of the Imc Macromentioning

confidence: 99%

“…Finally, the AVG lines will be sent to SAs to convert them into 1-bit output results. For more details, see [17]. Due to this analog computing for multiply and average (MAV), IMC has some model design limitations and non-ideal effects as shown below.…”

Section: Design For Non-ideal Effects Of the Imc Macromentioning

confidence: 99%