A reconfigurable real‐time neuromorphic hardware for spiking winner‐take‐all network

Abstract

The central nervous system receives a vast amount of sensory inputs, and it should be able to discriminate and recognize different kinds of multisensory information. Winner-take-all (WTA) consists of a simple recurrent neural network carrying out discrimination of input signals through competition. This paper presents a real-time scalable digital hardware implementation of the spiking WTA network. The need for concurrent computing, real-time performance, proper accuracy, and the reconfigurable device has led to the fieldprogrammable gate array (FPGA) as the target hardware platform. A set of techniques is employed to lessen memory and resource usage. The proposed architecture consists of multiprocessing elements, which share hardware resources between a specific number of neurons. We introduce a novel connectivity array for neurons (dedicated to the WTA network) to cut down memory usage. Also, a multiplier-less method in the neuron model and a novel tree adder in the synapse processing unit are designed to improve computational efficiency. The proposed network simulates 4,500 neurons in real time on a Xilinx Artix-7 FPGA, while a scalable architecture facilitates the implementation of up to 20,000 neurons on this device. The pipeline structure can guarantee real-time performance for large-scale networks. Based on simulation and physical synthesis results, the presented network mimics biological WTA dynamics and consumes efficient hardware resources.

Reconfigurable multivalued memristor FPGA model for digital recognition

“…Digital emulators also attract many researchers due to their small area, hardware flexibility, reconfigurability, and ease of programming and control. [10][11][12][13][14][15][16][17] Few schemes have been proposed for low-power, reconfigurable memristor models in the literature. In Tolba et al, 12 two discrete and continuous versatile memristor models alongside their FPGA realizations are proposed.…”

“…The analog circuit emulator builds modeling equations based on the memristor's experimental data, which match the physical properties of the memristor. Digital emulators also attract many researchers due to their small area, hardware flexibility, reconfigurability, and ease of programming and control 10–17 …”

Reconfigurable field‐programmable gate array‐based on‐chip learning neuromorphic digital implementation for nonlinear function approximation

“…Moreover, the logic capacity of FPGA to implement complex neural algorithms and prototypes without requiring VLSI chip fabrication makes it a brilliant choice. [19][20][21][22][23][24][25][26][27][28][29][30][31] FPGA-based on-chip learning and off-chip learning, which are sometimes known as online learning and offline learning, are the main methods for learning implementation in the hardware at register transfer level (RTL). 26,27 Motivated by these findings, this paper proposes an efficient and high-speed reconfigurable digital implementation of an SNN using Izhikevich neurons and gradient descent learning on an FPGA to approximate the sigmoid function.…”

An equivalent electrical circuit for the Hindmarsh‐Rose model

“…In contrast to the original Hodgkin‐Huxley and Morris‐Lecar model, the more abstract models can, for example, also exhibit a bursting behavior being observed from certain neuron types 14 . The Izhikevich model is especially popular in the context of field programmable gate array (FPGA) realizations, 16–18 while the Hindmarsh‐Rose model is either realized by integrator circuits 19–21 or digitally by FPGAs 22 …”