A reconfigurable stochastic architecture for highly reliable computing

Abstract

Mounting concerns over variability, defects and noise motivate a new approach for integrated circuits: the design of stochastic logic, that is to say, digital circuitry that operates on probabilistic signals, and so can cope with errors and uncertainty. Techniques for probabilistic analysis are well established. We advocate a strategy for synthesis. In this paper, we present a reconfigurable architecture that implements the computation of arbitrary continuous functions with stochastic logic. We analyze the sources of error: approximation, quantization, and random fluctuations. We demonstrate the effectiveness of our method on a collection of benchmarks for image processing. Synthesis trials show that our stochastic architecture requires less area than conventional hardware implementations. It achieves a large speed up compared to software conventional implementations. Most importantly, it is much more tolerant of soft errors (bit flips) than these deterministic implementations.

Survey of Stochastic Computing

“…The stochastic number's value p is carried by the number of 1s in its bit-stream form, so it suffices to count these 1s in order to extract p. Figure 3(b) shows a counter that performs this conversion. Figure 4 shows a stochastic circuit that implements the arithmetic function z = [Li et al 2009]. The inputs x 1 , x 2 , x 3 , and x 4 are provided in conventional binary form and must be converted to stochastic numbers via SNGs.…”

Probabilistic analysis of dynamic and temporal fault trees using accurate stochastic logic gates

“…In stochastic logic, inputs are vectors in which the number of 1 in each vector represents the given probability and computations are performed using logical hardware gates. Vectors can process each gate in serial or in parallel [26] and these values provide the corresponding probability of the inputs [28]. The values of stochastic logic are binary [29], which means that the probability is provided by dividing the number of 1-value bits by the total number of bits in the stream [26].…”

“…If the inputs of the AND gate are bits, it will AND the bits logically as the stochastic logic [28]. In an OR gate, one input or more must fail to make the top event of the gate to occur [6].…”

A Native Stochastic Computing Architecture Enabled by Memristors

“…5 [34]. The randomization cost presents a significant overhead in stochastic computing, sometimes as high as 80% of the total resource usage [35].…”

“…Despite the slow progress, continued research has made the following advances: 1) a large collection of logic, arithmetic, and matrix operations can now be done in stochastic computing [34]- [39], all of which share the elegance of very simple designs and 2) special applications, including artificial neural networks [40]- [42], image processing [35], [43], and decoding of low-density parity-check codes [44], [45] have been successfully demonstrated using stochastic computing. Note the common characteristics among these special applications: 1) error-tolerant and 2) compute-intensive, and the low-cost stochastic computing promises substantial reduction in complexity.…”