A recursive carry-lookahead/carry-select hybrid adder

Kantabutra, Vitit

doi:10.1109/12.260639

Cited by 53 publications

(24 citation statements)

References 14 publications

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“…It consists of 14 4-bit blocks and some logic gates, then 2758 transistors are required. Therefore, with respect to the circuit proposed in De Gloria and Olivieri (1996) It is worth pointing out that the maximum delay of the proposed 56-bit self-timed adder is about 18 ns which is largely worse than that shown by synchronous adders (Kantabutra 1993). It occurs when all p 0 i are low.…”

Section: Resultsmentioning

confidence: 90%

A new high performance circuit for statistical carry lookahead addition

Corsonello¹,

Perri²,

Cocorullo³

1999

International Journal of Electronics

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This paper presents a new e cient VLSI implementation of a variable-time adder based on the statistical carry lookahead addition technique. As opposed to a previous proposal, the new circuit does not require precharged input signals. Therefore, it can be used in practical asynchronous system design and in mixed logic design without any auxiliary circuitry. For this reason, such implementation reduces power dissipation. The circuit is realized in domino logic and for the critical path DCVSL (di erential cascode voltage switch logic) gates are used. A similar designed 56-bit adder requires 2758 transistors and shows an average delay of about 1.59 ns using MOSIS 0.5 m m technology.

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Section: Resultsmentioning

confidence: 90%

A new high performance circuit for statistical carry lookahead addition

Corsonello¹,

Perri²,

Cocorullo³

1999

International Journal of Electronics

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“…For the sake of comparison that design has been purposely laid out using 0.35 mm CMOS and it was enclosed in the test chip of figure 5. Also, a 56-bit Kantabutra-style adder (Kantabutra 1993), provided with an appropriate end-completion network matching the worst-case delay has been realized using the same standard cell library. Kantabutra's adder represents one of the fastest fixed-time addition circuits and has led to a fast but expensive and power hungry bounded-delay adder.…”

Section: Post-layout Simulation Resultsmentioning

confidence: 99%

“…The new circuit can easily migrate to the newest low-voltage CMOS process, and further advantages are expected. Kantabutra (1993). 3 Ruiz (1998).…”

Section: Discussionmentioning

confidence: 98%

An efficient self-timed adder realized using conventional CMOS standard cells

Perri

Corsonello

Cocorullo

2003

International Journal of Electronics

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Usually, efficient self-timed adders are realized using the dynamic differential cascode voltage switch logic. This allows the end-completion to be easily detected, but it makes circuit design and testing very complex, compelling the production of full-custom layouts and leading to a very long time before marketing. This paper presents a new 56-bit high-speed self-timed adder realized with conventional AMS 0.35 mm CMOS standard cells. The proposed circuit uses overlapped execution circuits, which exploit the initialization time that always elapses between two consecutive addition operations. Compared to several self-timed adders existing in the literature, the addition circuit proposed here shows brilliant advantages in terms of speed-performance, silicon area occupancy and power dissipation.

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“…Optimization of speed, area or power of adders is crucial for the design. Many hybrid designs of adders have been proposed, which discusses how to tradeoff area, power or speed by combining two or more types of adder [1], [5]. When tradeoff is performed on one parameter, might degrade the other parameters [6].…”

Section: Introductionmentioning

confidence: 99%