A Register Allocation Algorithm in the Presence of Scalar Replacement for Fine-Grain Configurable Architectures

Baradaran, Nastaran; Diniz, Pedro C.

doi:10.1109/date.2005.35

Cited by 21 publications

(19 citation statements)

References 13 publications

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“…As far as register the allocation problem is concerned, many methodologies exist such as [34] [40]. In [34] - [38], data reuse is not taken into account.…”

Section: Related Workmentioning

confidence: 99%

“…In [34] - [38], data reuse is not taken into account. In [39] and [40], data reuse is taken into account either by greedily assigning the available registers to the data array references or by applying loop unroll transformation to expose reuse and opportunities for maximizing parallelism. In [41], a survey on combinatorial register allocation and instruction scheduling is given.…”

Section: Related Workmentioning

confidence: 99%

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A methodology pruning the search space of six compiler transformations by addressing them together as one problem and by exploiting the hardware architecture details

Kelefouras

2017

Computing

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Today's compilers have a plethora of optimizations-transformations to choose from, and the correct choice, order as well parameters of transformations have a significant/large impact on performance; choosing the correct order and parameters of optimizations has been a long standing problem in compilation research, which until now remains unsolved; the separate subproblems optimization gives a different schedule/binary for each sub-problem and these schedules cannot coexist, as by refining one degrades the other. Researchers try to solve this problem by using iterative compilation techniques but the search space is so big that it cannot be searched even by using modern supercomputers. Moreover, compiler transformations do not take into account the hardware architecture details and data reuse in an efficient way.In this paper, a new iterative compilation methodology is presented which reduces the search space of six compiler transformations by addressing the above problems; the search space is reduced by many orders of magnitude and thus an efficient solution is now capable to be found. The transformations are the following: loop tiling (including the number of the levels of tiling), loop unroll, register allocation, scalar replacement, loop interchange and data array layouts. The search space is reduced a) by addressing the aforementioned transformations together as one problem and not separately, b) by taking into account the custom hardware architecture details (e.g., cache size and associativity) and algorithm characteristics (e.g., data reuse).The proposed methodology has been evaluated over iterative compilation and gcc/icc compilers, on both embedded and general purpose processors; it achieves significant performance gains at many orders of magnitude lower compilation time.

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“…As far as register the allocation problem is concerned, many methodologies exist such as [34] [40]. In [34] - [38], data reuse is not taken into account.…”

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

A methodology pruning the search space of six compiler transformations by addressing them together as one problem and by exploiting the hardware architecture details

Kelefouras

2017

Computing

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“…Approaches in [14] and [15] determine which data should be transferred into SPM and when and where in a code these transfers happen to improve the performance of the code, based on memory access cost models. Research into buffering reused data in FPGA on-chip RAMs and registers has been carried out in [5], [7], [8], and [16]. In [16], applications speed up through pipelining with high data throughput, which is obtained by storing reused data in shift registers and shift on-chip RAMs.…”

Section: Introductionmentioning

confidence: 99%

“…In [16], applications speed up through pipelining with high data throughput, which is obtained by storing reused data in shift registers and shift on-chip RAMs. In [7] and [8], arrays more beneficial to minimize the memory access time are stored in either registers or on-chip RAMs if register is not available. The work in [5] formulates the problem of data-reuse exploration aimed at low power as the multichoice knapsack problem.…”

Section: Introductionmentioning

confidence: 99%

“…Because different sets of loop iterations may access the same data (data reuse), every dual-port RAM bank holds a copy of buffered data and is accessed by two PUs through its two ports. In this paper, registers are not used as on-chip data-reuse buffers, although the proposed framework could be combined with a register-oriented work [7]. Therefore, in this paper, the on-chip memory cost is measured in units of atomic on-chip embedded RAM blocks.…”

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confidence: 99%

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Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework

Liu

Constantinides

Masselos

et al. 2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-A nonlinear optimization framework is proposed in this paper to automate exploration of the design space consisting of data-reuse (buffering) decisions and loop-level parallelization, in the context of field-programmable-gate-array-targeted hardware compilation. Buffering frequently accessed data in on-chip memories can reduce off-chip memory accesses and open avenues for parallelization. However, the exploitation of both data reuse and parallelization is limited by the memory resources available on-chip. As a result, considering these two problems separately, e.g., first exploring data reuse and then exploring data-level parallelization, based on the data-reuse options determined in the first step, may not yield the performance-optimal designs for limited on-chip memory resources. We consider both problems at the same time, exposing the dependence between the two. We show that this combined problem can be formulated as a nonlinear program and further show that efficient solution techniques exist for this problem, based on recent advances in optimization of so-called geometric programming problems. The results from applying this framework to several real benchmarks implemented on a Xilinx device demonstrate that given different constraints on on-chip memory utilization, the corresponding performanceoptimal designs are automatically determined by the framework. We have also implemented designs determined by a two-stage optimization method that first explores data reuse and then explores parallelization on the same platform, and by comparison, the performance-optimal designs proposed by our framework are faster than the designs determined by the two-stage method by up to 5.7 times.

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Applied Reconfigurable Computing

Cardoso¹

2019

Lecture Notes in Computer Science

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A Register Allocation Algorithm in the Presence of Scalar Replacement for Fine-Grain Configurable Architectures

Abstract: Abstract

Cited by 21 publications

References 13 publications

A methodology pruning the search space of six compiler transformations by addressing them together as one problem and by exploiting the hardware architecture details

A methodology pruning the search space of six compiler transformations by addressing them together as one problem and by exploiting the hardware architecture details

Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework

Applied Reconfigurable Computing

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