A Register File Architecture and Compilation Scheme for Clustered ILP Processors

Abstract

Abstract. In Clustered Instruction-level Parallel (ILP) processors, the function units are partitioned and resources such as register file and cache are either partitioned or replicated and then grouped together into onchip clusters. We present a novel partitioned register file architecture for clustered ILP processors which exploits the temporal locality of references to remote registers in a cluster and combines multiple inter-cluster communication operations into a single broadcast operation using a new sendb instruction. Our scheme makes use of a small Caching Register Buffer (CRB) attached to the traditional partitioned local register file, which is used to store copies of remote registers. We present an efficient code generation algorithm to schedule sendb operations on-the-fly. Detailed experimental results show that a windowed CRB with just 4 entries provides the same performance as that of a partitioned register file with infinite non-architected register space for keeping remote registers.

CARS: a new code generation framework for clustered ILP processors

“…In this paper we assume a partitioned register file architecture with local register files containing registers with unique/private name space. However, our scheme can be easily adapted for replicated register file architectures as well [26]. We assume that an OP can only write to its local register file and an explicit inter-cluster copy OP is needed to access a register from a remote cluster.…”

“…We also identify and flag loop-invariant DEFs, back-edge DEFs and loop-join-DEFs of nodes in loops. This information will be used by CARS, for example to eliminate copy OPs along the back-edges of loops [27,26]. Physical registers are treated as a resource in CARS.…”

“…To avoid pseudo name dependencies we select registers for assignment in a round-robin fashion using an efficient data structure [26]. This data structure also allows us to quickly search for dead registers in a cluster.…”

“…Also, a register from the set of registers that are marked as dead in lcl reg bv but live in glbl reg bv may be allocated to a DEF, if the DEF is not live beyond the current region and the register does not belong to the set of preferred registers of all© s at the exits of the region. All of the above logic can be implemented by a set of logical operations on bit-vectors [26]. The¨s of a join node require copy OPs along its incoming edges if all of its predecessor© s were not allocated to the same register (see the example in figure 3).…”

“…Therefore, the complexity of our on-the-fly register allocation scheme is linear in number of nodes scheduled. Spilling: If none of the OPs in the ready listcan be scheduled due to lack of dead registers, then a live register is selected for spilling based on a set of heuristics [26]. In order to spill the selected register, a spill store OP is inserted in the DFG as a new USE of the DEF mapped to the register.…”