A Reliability-Aware Partitioner for Multi-FPGA Platforms

Design of Hardened Embedded Systems on Multi-FPGA Platforms

“…The reliability-aware partitioning task redistributes the independently recoverable areas among the available FPGAs by taking into account also possible recovery actions needed during the system's lifetime [Bolchini and Sandionigi 2011]. It reserves a suitable spare region for relocations.…”

“…When an error is signaled from the monitored FPGA, the fault classifier identifies it as recoverable or nonrecoverable by implementing the algorithm proposed in Bolchini and Sandionigi [2011]. The classification is based on the analysis of the fault's frequency.…”

“…The definition of the IRAs hosted on each device has been modeled as a mixed-integer linear programming (MILP) problem whose inputs are the nominal circuit (in terms of components and required resources) and the parameter max areas identified by the previous activity. A different approach to design space exploration for the identification of the most convenient solution in the partitioning of the system onto a single FPGA has been proposed in Bolchini and Sandionigi [2011], by means of a two-level engine based on genetic algorithms. Here, we adopt the MILP formulation to identify the most convenient solution, presenting a comparison with the one obtained from the other approach in Section 8.3.…”

“…Thus, it is necessary to detect faults affecting the controller and to guarantee the correctness of the reconfiguration process. Particular attention has been devoted to the fault classifier (for which different hardened implementations have been analyzed) for the criticality of the classification task as described in Bolchini and Sandionigi [2011]. A self-checking implementation based on the application of error detection codes has been selected, leading to a competitive solution characterized by acceptable costs and benefits in terms of reliability.…”