A Resolution Control Loop for TDC-Based Phase Detectors in ADPLLs

Abstract

This paper proposes a resolution control loop that runs in background to control the time resolution of a mid-rise Time to Digital Converter (TDC) used as a phase detector in All-Digital Phase Locked Loops (ADPLLs). The proposed resolution control loop minimizes the TDC resolution until the TDC linear dynamic range equals the range of the input time error. Consequently, PLL in-band phase noise is reduced due to reduction of the Power Spectral Density (PSD) of the TDC quantization noise. Moreover, the linearity of the TDC transfer function across the range of the input time error is guaranteed. On contrary, the counterpart resolution control loop based on Lloyd-Max algorithm does not guarantee the linearity of the TDC transfer function across the range of the input time error. Furthermore, the proposed resolution control loop achieves TDC quantization noise with a lower variance compared to that achieved by the counterpart resolution control loop when applied with a TDC with more than 3 bits. Finally, the hardware implementation of the proposed resolution control loop is more area and power efficient compared to the implementation of the counterpart resolution control loop.

Phase Locked-Loop Design of High-Order Automotive Frequency Modulated Continuous Wave Radar Based on Fast Integration Structure

“…Because the pulse train low-pass filter counting method is a relatively complex nonlinear processing method, it is difficult to make a linear approximation. Therefore, the analysis method of the system transfer function cannot be used to determine the design parameters of the phase-locked loop, and the decoupling control and analysis of the high-order digital phase-locked loop performance indicators cannot be realized, which cannot meet the high application requirements [12], [13].…”