A Resonant Tunneling Nanowire Field Effect Transistor with Physical Contractions: A Negative Differential Resistance Device for Low Power Very Large Scale Integration Applications

A 16-nm-Lg p-type Gate-all-around (GAA) silicon nanowire (Si NW) metal oxide semiconductor field effect transistor (MOSFET) was fabricated based on the mainstream bulk fin field-effect transistor (FinFET) technology. The temperature dependence of electrical characteristics for normal MOSFET as well as the quantum transport at cryogenic has been investigated systematically. We demonstrate a good gate-control ability and body effect immunity at cryogenic for the GAA Si NW MOSFETs and observe the transport of two-fold degenerate hole sub-bands in the nanowire (110) channel direction sub-band structure experimentally. In addition, the pronounced ballistic transport characteristics were demonstrated in the GAA Si NW MOSFET. Due to the existence of spacers for the typical MOSFET, the quantum interference was also successfully achieved at lower bias.

Section: Introductionmentioning

confidence: 99%

Cryogenic Transport Characteristics of P-Type Gate-All-Around Silicon Nanowire MOSFETs

Zhang

et al. 2021

“…Comparing with remote plasma and QALE, the selectivity to SiO2 is lower, but it has obvious advantages in etching anisotropy, which is crucial to control the accuracy of the final thickness of inner spacer. 3 Data of special method-typical remote downstream plasma 4 Data of special method-typical quasi-atomic layer etching 5 Related data are unknown…”

Section: Effect Of Pressure On Inner Spacer Etchingmentioning

confidence: 99%

Study of Silicon Nitride Inner Spacer Formation in Process of Gate-all-around Nano-Transistors

Zhou

et al. 2020

Stacked SiGe/Si structures are widely used as the units for gate-all-around nanowire transistors (GAA NWTs) which are a promising candidate beyond fin field effective transistors (FinFETs) technologies in near future. These structures deal with a several challenges brought by the shrinking of device dimensions. The preparation of inner spacers is one of the most critical processes for GAA nano-scale transistors. This study focuses on two key processes: inner spacer film conformal deposition and accurate etching. The results show that low pressure chemical vapor deposition (LPCVD) silicon nitride has a good film filling effect; a precise and controllable silicon nitride inner spacer structure is prepared by using an inductively coupled plasma (ICP) tool and a new gas mixtures of CH2F2/CH4/O2/Ar. Silicon nitride inner spacer etch has a high etch selectivity ratio, exceeding 100:1 to Si and more than 30:1 to SiO2. High anisotropy with an excellent vertical/lateral etch ratio exceeding 80:1 is successfully demonstrated. It also provides a solution to the key process challenges of nano-transistors beyond 5 nm node.

“…Tunneling field-effect transistors (TFETs) have arisen as promising devices with emerging device concepts by breaking through the subthreshold swing limit of 60 mV/dec for low-power applications [4][5][6]. GAA nanowire TFETs have become candidates for substitutes for conventional MOS technology, especially in terms of their energy efficiency and scaling due to the better electrostatic control of the tunneling carriers provided by their nanowire structure [7][8][9][10]. SiGe channel materials have been introduced due to their excellent bandgap, high mobility, high density of states, and high compatibility with existing CMOS technology [11,12].…”

Section: Introductionmentioning

confidence: 99%

The Effect of Doping on the Digital Etching of Silicon-Selective Silicon–Germanium Using Nitric Acids

Zhu

Kong

et al. 2021

Gate-all-around (GAA) field-effect transistors have been proposed as one of the most important developments for CMOS logic devices at the 3 nm technology node and beyond. Isotropic etching of silicon–germanium (SiGe) for the definition of nano-scale channels in vertical GAA CMOS and tunneling FETs has attracted more and more attention. In this work, the effect of doping on the digital etching of Si-selective SiGe with alternative nitric acids (HNO3) and buffered oxide etching (BOE) was investigated in detail. It was found that the HNO3 digital etching of SiGe was selective to n+-Si, p+-Si, and intrinsic Si. Extensive studies were performed. It turned out that the selectivity of SiGe/Si was dependent on the doped types of silicon and the HNO3 concentration. As a result, at 31.5% HNO3 concentration, the relative etched amount per cycle (REPC) and the etching selectivity of Si0.72Ge0.28 for n+-Si was identical to that for p+-Si. This is particularly important for applications of vertical GAA CMOS and tunneling FETs, which have to expose both the n+ and p+ sources/drains at the same time. In addition, the values of the REPC and selectivity were obtained. A controllable etching rate and atomically smooth surface could be achieved, which enhanced carrier mobility.