A Resource-Limited Hardware Accelerator for Convolutional Neural Networks in Embedded Vision Applications

Moini, Shayan; Alizadeh, Bijan; Emad, Mohammad; Ebrahimpour, Reza

doi:10.1109/tcsii.2017.2690919

Cited by 68 publications

(44 citation statements)

References 6 publications

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“…Because of the simpler operation circuits, the Fixed representation, especially of 16 bits, has been usually adopted in the field of ASIC or FPGA accelerator implementations [7,8,9,10]. The studies focusing on the representation format, on the other hand, have tried various representations including the Fixed representations, power-of-two representation, and shared values.…”

Section: Representation Widthmentioning

confidence: 99%

“…However, the deep structure requires an enormous amount of operations and storage, which make it hard to adopt CNNs to embedded devices. To overcome the limit of the embedded devices, there have been many studies to implement CNN accelerators in ASIC or FPGA [7,8,9,10].…”

Section: Introductionmentioning

confidence: 99%

“…Previous studies, especially on ASIC or FPGA implementation, have usually exploited the 16-bit fixed-point representation because the fixed-point representation is believed to produce simpler operation circuits than the floating-point representation [7,8,9,10]. Some other studies have focused on employment of different number representations for implementation of CNNs including shorter fixed-point representation [11,12,13,14,15,16] and simpler representations like binary or ternary representations [17,18].…”

Section: Introductionmentioning

confidence: 99%

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Short floating-point representation for convolutional neural network inference

Kang

2019

IEICE Electron. Express

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Convolutional neural networks (CNNs) are being widely used in computer vision tasks, and there have been many efforts to implement CNNs in ASIC or FPGA for power-hungry environments. Instead of the previous common representation, the fixed-point representation, this letter proposes a short floating-point representation for CNNs. The short floating-point representation is based on the normal floating-point representation, but has much less width and does not have complex cases like Not-a-Number and infinity cases. The short floating-point representation, contrary to the common belief, can produce a low-complexity computation logic because the operands of the multiplier logic can be shortened by the exponent concept of the floatingpoint representation. The exponent can also reduce the total length to reduce the SRAM area. The experimental results show that the short floating-point representation with 8-bit total width achieves less-than-1-percentage-point degradation without the aid of retraining in the top-5 accuracy on very deep CNNs of up to 152 layers and gives more than a 60% area reduction in the ASIC implementation.

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Section: Representation Widthmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Short floating-point representation for convolutional neural network inference

Kang

2019

IEICE Electron. Express

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“…PCANet is relatively new, and this work is, to the best of our knowledge, one of the first hardware implementations of PCANet. This work is related to the existing hardware implementations of CNNs [13,14].…”

Section: Related Workmentioning

confidence: 99%

“…Implementing a six-layer convolutional neural network requires 10 watts on a Xilinx Virtex-6 VLX240T board [21]. A state-of-the-art FPGA implementation achieves 10 fps with less than 10 watts power consumption [14].…”

Section: Comparison With Convolutional Neural Networkmentioning

confidence: 99%

VLSI design of a power-efficient object detector using PCANet

Zhou

Huang

2018

IEICE Electron. Express

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This paper presents the hardware architecture and VLSI implementations of a PCANet-based object detector. The proposed PCANet model, cascaded with a linear support vector machine, can achieve better classification performance than traditional handcrafted computer vision methods, yet it is significantly more power efficient than multi-layer convolutional neural networks. The proposed pipeline hardware architecture, when implemented using Synopsys 32 nm process technology, results in 27.4 fps while processing 1080P, with only 0.5 watt power consumption. Targeted for the application of advanced driver assistance system, the proposed design is evaluated on road marking and traffic light dataset with an accuracy result of 96.8% and 93.1% respectively. Therefore, the proposed VLSI implementation of PCANet algorithm provides a high-throughput and power-efficient solution for object detection applications.

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Efficient Implementation of Recurrent Neural Network Accelerators

Abdolzadeh

Petra

2019

Lecture Notes in Electrical Engineering

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A Resource-Limited Hardware Accelerator for Convolutional Neural Networks in Embedded Vision Applications

Cited by 68 publications

References 6 publications

Short floating-point representation for convolutional neural network inference

Short floating-point representation for convolutional neural network inference

VLSI design of a power-efficient object detector using PCANet

Efficient Implementation of Recurrent Neural Network Accelerators

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