A resume-standby application processor for 3G cellular phones

Kamei, Takeshi; Itō, Makoto; Hiraoka, Toshiro; Irita, Takahiro; Abe, Minoru; Saito, Yusaku; Tawara, Yasuhiro; Ide, H.; Furuyama, M.; Tamaki, Shigeru; Yasu, Y.; Shimazaki, Yasuhisa; Yamaoka, M.; Mizuno, Hiroyuki; Irie, Naohiko; Nishii, O.; Arakawa, Fumio; Hirose, Keikichi; Yoshioka, Shinichi; Hattori, Toshihiro

doi:10.1109/isscc.2004.1332731

Cited by 35 publications

(11 citation statements)

References 2 publications

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“…This tool allows analyzing system activities and benchmarking its performance at a cycle-approximate level. Our platform is assumed to operate within a supply voltage (V dd) range of 1 to 1.45 V according to various 90 nm system-on-chips used for mobile applications [14] [15]. The power consumption is estimated at high level to allow for relative power comparisons between various AES implemen tations.…”

Section: S Ystem P Rototy Pe and P Rofilingmentioning

confidence: 99%

High-performance and energy-efficient sliced AES multi-block encryption for LTE mobile devices

Traboulsi

Sbeiti

Szczesny

et al. 2011

2011 IEEE 3rd International Conference on Communication Software and Networks

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In this paper we present an efficient software im plementation of the Advanced Encryption Standard (AES) used in the confidentiality algorithm of the Long Term Evolution (LTE) protocol. Our implementation is based on slicing and merging the bytes of several data blocks to exploit processor's architecture width for multi-block encryption. In addition, an appropriate lookup table and data organization in memory are applied, combined with media processing instructions in order to enhance the performance of AES in embedded environments.Other optimized software implementations from literature are also explored and evaluated in comparison to the proposed implementation with respect to processing throughput and energy consumption using a multi-core based mobile phone platform.Simulation results show that the proposed implementation is the fastest among other implementations and achieves improvements in performance up to 69 % while providing S9 % of energy savings. Moreover, the presented implementation is scalable for multi-core execution. When running on two cores, it fulfills the LTE data rate of 100 Mbitls and extends energy savings to 68%, leading to a total of 13 times improvement in energy efficiency. I. I NTRODUCTIONThe speed of data transfer in mobile networks is continu ously increasing, reaching up to 100 Mbitls in the upcoming Long Term Evolution (LTE) standard. Security in cellular communication systems is based on cryptographic algorithms to encrypt and decrypt user data. These algorithms are com putationally expensive and require relatively long execution times. A former performance analysis of the LTE protocol stack in [1] identified ciphering as a time critical function. Thus providing an efficient ciphering implementation has a great impact on overall system performance. The energy consumption of software plays also a vital role in mobile devices due to its limited battery capacity.Ciphering algorithms in mobile handsets are typically ac celerated by dedicated hardware. Software implementations, however, enable sharing of computing resources between ci phering and other communication functionalities. In addition, it provides flexibility needed to support multiple cellular stan dards using different ciphering schemes. However, software implementations are relatively slow and therefore have to be efficient enough in order to fulfill the required timing constraints while consuming lowest energy possible. In this paper we introduce a novel software implementation of the confidentiality algorithm used in the LTE standard. The pro posed implementation exploits the processor architecture width to perform several ciphering operations simultaneously. As 978-1-61284-486-2/111$26.00 ©2011 IEEE embedded multi-core processors are expected to be deployed in future mobile devices [2], we also investigate how further speedups can be obtained by using multi-core processing. Fi nally, our implementation is evaluated against other optimized implementations from literature with respect to processing throughput and energy c...

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Section: S Ystem P Rototy Pe and P Rofilingmentioning

confidence: 99%

High-performance and energy-efficient sliced AES multi-block encryption for LTE mobile devices

Traboulsi

Sbeiti

Szczesny

et al. 2011

2011 IEEE 3rd International Conference on Communication Software and Networks

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“…The low-power version was integrated into an application processor for cellular phones. It runs at 200 MHz with a supply voltage of 1.0 V under worst-case conditions, achieving 360 MIPS and 80 mW measured using Dhrystone 2.1, and resulting in 4500 MIPS/W [7]. It integrates the DSP as a coprocessor, and maintains the code compatibility with the SH3-DSP.…”

Section: Sh-x Core Specificationsmentioning

confidence: 99%

“…The SH-Mobile, integrated with the new SH-X, incorporates power switches to partially cut off the internal power supply. It then implements a resume-standby mode to reduce the standby power, which is important for cellular phone processors [7]. In the resume-standby mode, the contents of some on-chip RAMs and specified control registers are retained, while the other internal power supplies are cut off, thus causing the leakage current to drop to 100 µA.…”

Section: Split Transaction Busmentioning

confidence: 99%

Development of processor cores for digital consumer appliances

Arakawa

Yamada

Okada

et al. 2006

Systems & Computers in Japan

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SUMMARYEmbedded processors are increasingly being used in digital consumer appliances such as cellular phones, digital still/video cameras, and car navigation systems. They must therefore deliver high performance within a reasonable area and power consumption level, and be flexible to meet a wide range of requirements for various applications. In this paper, we introduce our latest processor core SH-X developed under the above background. The low-power version of the SH-X core achieves 360 MIPS with a power of 80 mW resulting in the high power-performance ratio of 4500 MIPS/W. The standard version achieves 720 MIPS with a power of 250 mW, 2.8 GFLOPS, and 36M polygons/s graphics performance. The leak currents in the resume standby and U-standby modes are 100 and 10 µA, respectively. The resume standby mode can return the status before the standby in only 3 ms, while the U-standby mode requires reset sequence to restart.

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“…SuperH TM (SH) processor cores have an excellent power-performance ratio [3] [4]. Further, the floatingpoint performance of an SH processor core is as high as 5.6 GFLOPS, though this is for single-precision data [5][6] [7].…”

Section: Introductionmentioning

confidence: 99%

An Embedded Processor: Is It Ready for High-Performance Computing?

Arakawa

2007

Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA 2007)

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High power-performance ratio is the most important factor in high-performance computing, whose performance is limited by its power budget. A SuperH TM (SH) embedded processor core, SH-X3, implemented in a 90-nm CMOS process running at 600 MHz achieved 1080 Dhrystone MIPS, 4.2 GFLOPS, and 55M polygons/s. Its power performance ratio reaches to as high as 3000 MIPS/W. It is, therefore, a candidate processor for high-performance computing. This paper focuses on the SH processors' low power features, floating-point architecture and performance, and applicability to the highperformance computing.

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A resume-standby application processor for 3G cellular phones

Cited by 35 publications

References 2 publications

High-performance and energy-efficient sliced AES multi-block encryption for LTE mobile devices

High-performance and energy-efficient sliced AES multi-block encryption for LTE mobile devices

Development of processor cores for digital consumer appliances

An Embedded Processor: Is It Ready for High-Performance Computing?

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