A retargetable, ultra-fast instruction set simulator

Zhu, Jianwen; Gajski, Daniel D.

doi:10.1145/307418.307509

Cited by 59 publications

(29 citation statements)

References 8 publications

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“…Such translation can be done either at compile time (static compiled simulation), where the fetch-decode-dispatch overhead is completely eliminated, or at load time (dynamic compiled simulation), which amortises the overhead over repeated execution of code. Simulators based on the static compilation model are presented by Zhu and Gajski [44] and Pees et al [31]. Examples of dynamic compiled code simulators include the Shade simulator [45], and the Embra simulator [46].…”

Section: Simulatorsmentioning

confidence: 99%

Processor Description Languages

Mishra¹,

Dutt²

2008

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Embedded systems present a tremendous opportunity to customise designs by exploiting the application behaviour. Shrinking time-to-market, coupled with short product lifetimes, create a critical need for rapid exploration and evaluation of candidate architectures. Architecture description languages (ADL) enable exploration of programmable architectures for a given set of application programs under various design constraints such as area, power and performance. The ADL is used to specify programmable embedded systems, including processor, coprocessor and memory architectures. The ADL specification is used to generate a variety of software tools and models facilitating exploration and validation of candidate architectures. The paper surveys the existing ADLs in terms of (a) the inherent features of the languages and (b) the methodologies they support to enable simulation, compilation, synthesis, test generation and validation of programmable embedded systems. It concludes with a discussion of the relative merits and demerits of the existing ADLs and expected features of future ADLs.

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Section: Simulatorsmentioning

confidence: 99%

Processor Description Languages

Mishra¹,

Dutt²

2008

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“…In statically compiled approaches [7,35] dynamic decoding of target binary code is avoided. For example, SyntSim [7] is a simulator synthesizer, which generates statically compiled/interpretive mixed simulators.…”

Section: Fast Simulation Techniquesmentioning

confidence: 99%

“…In their approach, target binary can be translated into C language and further compiled to host instructions. Rather than using C language as a code generation interface, an improvement [35] is introduced, in which an aggressive low level code generation interface is used.…”

Section: Fast Simulation Techniquesmentioning

confidence: 99%

A fast and generic hybrid simulation approach using C virtual machine

Gao

Kraemer

Leupers

et al. 2007

Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems

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Instruction Set Simulators (ISSes) are important tools for cross-platform software development. The simulation speed is a major concern and many approaches have been proposed to improve the performance of ISSes. A prevalent technique is compiled simulation, which translates target programs into host instructions. But orders of magnitude of speed deterioration is inevitable since the difference between target and host Instruction Set Architectures (ISAs) can be large. An alternative is to emulate the program without sticking to binary compatibility. The performance problem is solved by using native execution. However, these emulators either require a special programming language, or a given Application Programming Interface (API). Last but not least, it is not trivial to integrate an emulator into a system simulator (which provides devices, external memory, etc., that the embedded programmers do care). In this paper, we propose a fast and generic hybrid simulation approach using virtualization technique to accelerate simulation and simulator-based debugging of C programs. A novel virtual coprocessor (VCP) is introduced as a processing element which executes C functions at high speed. This approach is C89 compliant and compatible with third party libraries and platform dependent code. It is also retargetable and can be integrated with existing ISSes. Two different ISAs are supported at present: MIPS and mAgic DSP. The average execution speed of the coprocessor is about 100 million simulated instructions per second.

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“…But the disadvantage is that the running speed is slow. When as, the compiled ISS, such as Static Compiled ISS [2] and Embra [3], translate the object binary system code into native machine binary system code. Running speed of the compiled ISS is 1 order of magnitudes faster than that of the explained ISS.…”

Section: Introductionmentioning

confidence: 99%

Design of SPARC V8 ISS Based on SystemC

Yang¹,

Feng²,

Yu³

2015

IJIEE

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Abstract-Nowadays System on Chip (SoC) coming into use everywhere, SoC simulators are developing rapidly. Instruction Set Simulator (ISS) is one of the most popularly used tools for SoC exploitation. SoC designers can use it to test and verify their new designed processors, design and verify compilers, assistant debugging systems, and evaluate operating systems. A SPARC V8 ISS model base on SystemC is established in this paper, and it has been used to exploit application program, replant BenchMark and test and verify Golden Model. Test results proved the validity of the model function. In addition, the model has flexible structure with variety functions and strong practicability, so it can make great effect when design processors.

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A retargetable, ultra-fast instruction set simulator

Abstract: In this paper, we present new techniques which further improve the static compiled instruction set architecture (ISA)

Cited by 59 publications

References 8 publications

Processor Description Languages

Processor Description Languages

A fast and generic hybrid simulation approach using C virtual machine

Design of SPARC V8 ISS Based on SystemC

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