A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks

Seo, Min-Jae; Roh, Yi-Ju; Chang, Dong Jin; Kim, Wan; Kim, Ye-Dam; Ryu, Seung‐Tak

doi:10.1109/tcsii.2018.2822811

Cited by 37 publications

(12 citation statements)

References 8 publications

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“…Moreover, the proposed ADC achieves a better Schreier FoM than those except for [28,30] under trading off among the linearity, power consumption and chip area. The area is smaller than [27] with the same process and resolution except for [29] due to its digital design flow.…”

Section: Measurement Resultsmentioning

confidence: 99%

Theoretical total harmonic distortion evaluation based on digital to analogue converter mismatch to improve the linearity of successive approximation register analogue to digital converter

Song

Zhang

et al. 2021

IET Circuits, Devices & Syst

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Mismatch in the binary-weighted capacitive digital-to-analog converter (DAC) greatly affects the linearity of the successive-approximation-register (SAR) ADC by deteriorating the total harmonic distortion (THD). In this study, a theoretical relationship between the THD and the mismatch error of DAC array in SAR ADC is derived through discrete Fourier transform (DFT) analysis of the time-based integral error (TIE) of the ADC's output codes, which has no specific requirement on the type of the input signals. Guided by the theoretical THD expression, the trade-off among the linearity, design complexity, power consumption and chip area can be balanced easily. The presented formula is verified by a design example of 12-bit SAR ADC with dynamic-element-matching (DEM) technique, where the 3-bit LSBs from the SAR ADC are used to generate the randomised DEM state according to the previous THD evaluation. The linearity is enhanced by 9 dB approximately with very low hardware complexity and extremely small extra power consumption of 2 μW. K E Y W O R D Sanalog-to-digital converter, dynamic element matching, successive approximation register, time-based integral error, total harmonic distribution This is an open access article under the terms of the Creative Commons Attribution-NonCommercial-NoDerivs License, which permits use and distribution in any medium, provided the original work is properly cited, the use is non-commercial and no modifications or adaptations are made.

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Section: Measurement Resultsmentioning

confidence: 99%

Theoretical total harmonic distortion evaluation based on digital to analogue converter mismatch to improve the linearity of successive approximation register analogue to digital converter

Song

Zhang

et al. 2021

IET Circuits, Devices & Syst

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“…While it is possible to implement metal-oxide-metal (MOM) sampling capacitors using SKILL language [29], [30] or p-cell initialization by the script in a digital P&R flow [22], to mitigate implementation complexity, and to explore the possibility of an all-standard-cell-based ADC, we implement the sampling capacitor using MOSFET gate capacitance in this work. As shown in Fig.…”

Section: Sample-and-hold (S/h) Circuitmentioning

confidence: 99%

“…The type of each cell is also shown in the figure. The difference from [30] is that the sampling capacitor is changed to a thick-oxide decoupling cell for less leakage. By keeping V ss port floating, the leakage is further suppressed, and the voltage-dependent capacitance variation is mitigated as well.…”

Section: Rdac Enabling Control and Bootstrapped S/h Circuit With Floa...mentioning

confidence: 99%

“…By registering custom-designed cells to a physical library, automatic P&R flows for analog circuits were introduced [17], [19], [23], [24], [28]. Also, hybrid methods for successive-approximation-register (SAR) ADCs were proposed with SKILL language for capacitive digitalto-analog converter (CDAC) generation [29], [30]. The two works have achieved high performance at the cost of more implementation complexity.…”

Section: Introductionmentioning

confidence: 99%

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An All-Standard-Cell-Based Synthesizable SAR ADC With Nonlinearity-Compensated RDAC

Ojima

et al. 2021

IEEE Trans. VLSI Syst.

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We propose an all-standard-cell-based synthesizable successive-approximation-register analog-to-digital converter (SAR ADC) which is automatically placed and routed (P&R) using a commercial digital implementation tool. For higher feasibility and wider input range, a differential architecture is proposed with an inverter-based resistive digital-to-analog converter (RDAC) and a four-input comparator. MOSFET gate capacitance is employed for the sampling capacitor. To mitigate its capacitance variation due to input voltage and the leakage between gate and diffusion, we leave the diffusion of the standard cell floating and only use the capacitance between gate and bulk. Two prototypes have been designed in 65-nm bulk CMOS. Prototype I has been fabricated and achieves 10 MS/s, 14.3 mW, and 28.1-dB SNDR in a 6-bit architecture. The performance is improved in Prototype II by proposing a lookup table (LUT)-compensating transistor-configurable inverter-based RDAC and an OR-AND-Inverter (OAI)-based comparator and by employing a thick-oxide diffusion-floating decoupling cell for the sampling capacitor. The default LUT is created during the design phase by a script-controlled automatic simulation routine. The power consumption is significantly reduced as well through improved timing control. Layout-parasitic-extraction (LPE) simulations of Prototype II suggest 35.7-and 47.2-dB SNDRs in 6-and 8-bit versions, respectively. The power consumptions are reduced to 0.91 and 2.52 mW, respectively.

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“…In addition, a distributed waveform monitoring system is needed because of the difficulty in implementing an analog signal buffer that can be operated with the low supply voltage. Thus, a compact active area with enhanced portability and reusability are important for realizing the distributed structure and reducing both the design time and the manufacturing cost [8]. Therefore, a synthesizable digital implementation of the on-chip waveform monitor has been preferred to satisfy those requirements.…”

Section: Introductionmentioning

confidence: 99%

A 0.5-V Fully Synthesizable SAR ADC for On-Chip Distributed Waveform Monitors

2019

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This paper presents a fully synthesizable successive-approximation-register (SAR) analog-todigital converter (ADC) for on-chip distributed waveform monitoring in a low-power system-on-chip (SoC). All blocks in the proposed ADC are designed using only standard digital cells, enabling an auto-generation based on regular digital design tools. Therefore, the proposed ADC provides enhanced portability and reusability which facilitate integration into various functional blocks requiring testing and diagnosis. To implement the SAR ADC, a synthesizable voltage digital-to-analog converter (VDAC) and a rail-torail hybrid comparator are proposed in this paper. An inherited nonlinearity of the standard-cell-based VDAC is compensated by a histogram-based soft calibration which can be easily embedded in a waveform reconstruction module. In addition, an oversampling technique with a redundant error correction method is employed to realize the fully synthesizable design without a sample-and-hold (S/H) circuit. The proposed ADC was fabricated in 28-nm CMOS technology, occupying an active area of 0.002 mm 2. The ADC achieves 5.39-bit effective-number-of-bit (ENOB) at 500-kS/s sampling rate. The power consumption of the ADC is 92.2 µW with a supply voltage of 0.5 V.

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A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks

Cited by 37 publications

References 8 publications

Theoretical total harmonic distortion evaluation based on digital to analogue converter mismatch to improve the linearity of successive approximation register analogue to digital converter

Theoretical total harmonic distortion evaluation based on digital to analogue converter mismatch to improve the linearity of successive approximation register analogue to digital converter

An All-Standard-Cell-Based Synthesizable SAR ADC With Nonlinearity-Compensated RDAC

A 0.5-V Fully Synthesizable SAR ADC for On-Chip Distributed Waveform Monitors

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