A Review of 3D-Dynamic Random-Access Memory based Near-Memory Computation

Ravichandiran, Prasanth Prabu; Franzon, Paul D.

doi:10.1109/3dic52383.2021.9687615

Cited by 6 publications

(2 citation statements)

References 33 publications

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“…switches are used to isolate the SA from the reference bitline and the precharge cir Though energy consumption in the precharge stage is inevitable, the voltage supply f the SA is not required to charge the BLB to VDD, thereby (VDD 2 Cb)/2 can be reduce the post-sense stage. Similarly, during a read '1′-write '0′ operation, there is no vol supply requirement for charging the BLB capacitance Cb from the write driver, resu in reduced VDD 2 Cb in the IO transition stage. The newly added switches can be contro by the least significant bit (LSB) of the row address line.…”

Section: Analysis Of the Single Bitline Load Sense Amplifiermentioning

confidence: 99%

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Low-Power Single Bitline Load Sense Amplifier for DRAM

Dai,

Lu,

et al. 2023

Electronics

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With the significant growth in modern computing systems, dynamic random access memory (DRAM) has become a power/performance/energy bottleneck in data-intensive applications. Both the power management mechanism and downscaling method face decreasing performance or difficulties in the smaller footprint of the DRAM capacitor. Since optimizing the circuit of sense amplifier (SA) is an efficient method to reduce energy consumption, we propose two single bitline load sense amplifier (SBLSA) circuits, i.e., a redundant voltage discharged SBLSA (RVD-SBLSA) circuit and a bit aware SBLSA (BA-SBLSA) circuit, to improve conventional and single bitline write (SBW) circuits. The RVD-SBLSA circuit utilizes a clamp diode to discharge redundant voltage over VDD/2 with an additional working stage. The BA-SBLSA circuit abandons the single bitline load (SBL) circuit during read and write ‘1’ operations. The RVD-SBLSA circuit can offer the lowest total energy consumption, and the BA-SBLSA circuit can make a better balance between energy consumption and latency. Through the simulation results, the proposed circuits can efficiently reduce energy consumption or balance energy consumption and latency and show huge potentials in very large-scale integrated circuits.

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Section: Analysis Of the Single Bitline Load Sense Amplifiermentioning

confidence: 99%

“…The volatile memory of static random access memory (SRAM) and dynamic random access memory (DRAM) are widely used in computing systems [1][2][3][4]. Scaling bulk CMOS SRAM technology for on-chip caches beyond the 22 nm node results in high leakage power consumption, performance degradation, and instability due to process variations [5,6].…”

Section: Introductionmentioning

confidence: 99%

Low-Power Single Bitline Load Sense Amplifier for DRAM

Dai,

Lu,

et al. 2023

Electronics

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SSA-over-array (SSoA): A stacked DRAM architecture for near-memory computing

Jiang,

Bai,

Wang

et al. 2024

J. Semicond.

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Aiming to enhance the bandwidth in near-memory computing, this paper proposes a SSA-over-array (SSoA) architecture. By relocating the secondary sense amplifier (SSA) from dynamic random access memory (DRAM) to the logic die and repositioning the DRAM-to-logic stacking interface closer to the DRAM core, the SSoA overcomes the layout and area limitations of SSA and master DQ (MDQ), leading to improvements in DRAM data-width density and frequency, significantly enhancing bandwidth density. The quantitative evaluation results show a 70.18 times improvement in bandwidth per unit area over the baseline, with a maximum bandwidth of 168.296 Tbps/Gb. We believe the SSoA is poised to redefine near-memory computing development strategies.

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