A review of fault models for lsi/vlsi devices

Gai, Shan; Mezzalama, Marco; Prinetto, P.

doi:10.1049/sm.1983.0016

Cited by 13 publications

(5 citation statements)

References 24 publications

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“…Faults are technology dependent [42], [43]. For example, logic gate bridging faults have different behavioral properties in TTL (wired-AND), ECL (wired-OR), and CMOS (wired-X), and the fault models take these into account [22], [44].…”

Section: Fault Detectionmentioning

confidence: 99%

I DDQ testing: A review

et al. 1992

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Quiescent power supply current (IDDQ) testing of CMOS integrated circuits is a technique for production quality and reliability improvement, design validation, and failure analysis. It has been used for many years by a few companies and is now receiving wider acceptance as an industry tool. This article begins with a brief history of CMOS ICs to provide perspective on the origin of IDD Q testing. Next, the use of [DDQ testing for IC quality improvement through increased defect and fault detection is described. Then implementation issues are considered, including test pattern generation software, hardware instrumentation, limit setting, IC design guidelines, and defect diagnosis. An extended reference list is provided to help the reader obtain more information on specific aspects.

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Section: Fault Detectionmentioning

confidence: 99%

I DDQ testing: A review

et al. 1992

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“…, s, ) (1) where ik is the kth input, sk is the kth state variable (for sequential circuits) and F is a generic logic function (for example AND, OR, SHIFT). 15 In faulty circuits the function Ff (the subscript f denotes variables in a faulty circuit) depends on .several parameters (temperature, humidity, time, manufacturing process etc.) in such a way that Uf differs from the output U of a fault-free circuit.…”

Section: Failure Mechanisms and Modesmentioning

confidence: 99%

“…A test is designed to detect in CMOS.5. 6,15,18 the presence of physical failures in a circuit, whereas a fault simulator measures the effectiveness of the test pattern set in terms of the number of failures it actually detects and computes the fault coverage for the given fault model. Since a simulator deals with a model of the physical system being simulated, the results are only as accurate as the model used in the simulation: The main tasks of a fault simulator, for a given set of test patterns, are summarized asw 1. calculation of expected output values 2. creation of a fault dictionary 3. calculation of the fault coverage.…”

Section: The Stuck-at Fault Modelmentioning

confidence: 99%

A two‐step methodology for CMOS VLSI reliability improvement: Step one

Davies

Miles

Postoyalko

1988

Quality & Reliability Eng

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Reliability improvement of CMOS VLSI circuits depends on a thorough understanding of the technology, failure mechanisms, and resulting failure modes involved. Failure analysis has identified open circuits, short circuits and MOSFET degradations as the prominent failure modes. Classical methods of fault simulation and test generation are based on the gate level stuck‐at fault model. This model has proved inadequate to model all realistic CMOS failure modes. An approach, which will complement available VLSI design packages, to aid reliability improvement and assurance of CMOS VLSI is outlined. A ‘two‐step’ methodology is adopted. Step one, described in this paper, involves accurate circuit level fault simulation of CMOS cells used in a hierarchical design process. The simulation is achieved using SPICE and pre‐SPICE insertion of faults (PSIF). PSIF is an additional module to SPICE that has been developed and is outlined in detail. Failure modes effects analysis (FMEA) is executed on the SPICE results and FMEA tables are generated. The second step of the methodology uses the FMEA tables to produce a knowledge base. Step two is essential when reliability studies of larger and VLSI circuits are required and will be the subject of a future paper. The knowledge base has the potential to generate fault trees, fault simulate and fault diagnose automatically.

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“…It was conceived for testing both combinational and sequential circuits described at the gate level with the 'single stuck-at' fault model. Different fault models [15,16] are not considered for two main reasons: either they require a transistor-level description of the network (for example stuck-at-open), or modification of the gate-level description is needed (for example bridging faults). In the first case, ATG algorithms are more complex and not well defined, while in the second case a different version of the network must be considered for each fault.…”

Section: Testability Measuresmentioning

confidence: 99%