A review of silicon carbide CMOS technology for harsh environments

Wang, Hui; Lai, Pengyu; Islam, Md Zahidul; Hasan, Abu Shahir Md Khalid; Di Mauro, Anthony; Anika, Nur-E-Afra; Russell, Robert; Feng, Zhuowen; Chen, Kevin; Faruque, Asif; White, Thomas; Chen, Zhong; Mantooth, H. Alan

doi:10.1016/j.mssp.2024.108422

Cited by 4 publications

(2 citation statements)

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“…Gate leakage I gss is tested with V GS = 22 V and V DS = 0 V, and V sd is tested with V GS = 0 V and I SD = 8.5 A. Combined with Figure 10a,b, for the DT-MOSFET, V th and R on sharply decrease to 3.9 V and 73 mΩ•cm 2 , respectively, at the beginning, and then as the cycles increase, the values remain almost unchanged. While, for the AT-MOSFET, these two electrical parameters almost keep constant after repetitive UIS pulses, which indicates that the gate oxide has been well protected by the P+ region in the source of the AT-MOSFET.…”

Section: Repetitive Avalanche Stressmentioning

confidence: 84%

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A Comprehensive Analysis of Unclamped-Inductive-Switching-Induced Electrical Parameter Degradations and Optimizations for 4H-SiC Trench Metal-Oxide-Semiconductor Field-Effect Transistor Structures

Liu,

Guo,

Shi

et al. 2024

Micromachines

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This paper presents a comprehensive study on single- and repetitive-frequency UIS characteristics of 1200 V asymmetric (AT) and double trench silicon carbide (DT-SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) and their electrical degradation under electrical–thermal working conditions, investigated through experiment and simulation verification. Because their structure is different, the failure mechanisms are different. Comparatively, the gate oxide of a DT-MOSFET is more easily damaged than an AT-MOSFET because the hot carriers are injected into the oxide. The parameters’ degradation under repetitive UIS stress also requires analysis. The variations in the measured parameters are recorded to evaluate typical electrical features of device failure. Furthermore, TCAD simulation is used to reveal the electrothermal stress inside the device during avalanche. Additionally, failed devices are decapsulated to verify the location of the failure point. Finally, a new type of stepped-oxide vertical power DT MOSFET with P-type shielding and current spread layers, along with its feasible process flow, is proposed for the improvement of gate dielectric reliability.

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Section: Repetitive Avalanche Stressmentioning

confidence: 84%

“…Due to its wide bandgap, highly critical breakdown electrical field, and thermal conductivity, SiC is recognized as the most promising candidate for high-temperature and high-power applications [ 1 , 2 , 3 ].…”

Section: Introductionmentioning

confidence: 99%