A review of the mechanical stressors efficiency applied to the ultra-thin body &amp; buried oxide fully depleted silicon on insulator technology

Morin, P.; Maîtrejean, S.; Allibert, F.; Augendre, E.; Liu, Qing; Loubet, N.; Grenouillet, L.; Pofelski, Alexandre; Chen, Kangguo; Khakifirooz, A.; Wacquez, R.; Reboh, S.; Bonnevialle, A.; Royer, C. Le; Morand, Y.; Kanyandekwe, J.; Chanemougamme, Daniel; Mignot, Yann; Escarabajal, Yann; Lherron, B.; Chafik, F.; Pilorget, S.; Caubet, P.; Vinet, M.; Clément, L.; DeSalvo, B.; Doris, B.; Kleemeier, W.

doi:10.1016/j.sse.2015.11.024

Cited by 9 publications

(3 citation statements)

References 93 publications

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“…It is demonstrated that ample control of SCEs achieved in FDSOI scaling down to 10 nm without performance degradation [78,79], benefiting from the inherent thin SOI architecture [80] and based on the investigation on SCEs [81], indicated that devices are still indomitable against SCEs even with a fairly thin SOI film [82]. Naturally, the leakage current into the substrate and gate-induced drain leakage (GIDL) current are largely lessened [83,84] thanks to the carriers being strictly confined within the thin channel.…”

Section: Fdsoi Salient Characteristicsmentioning

confidence: 99%

“…nm without performance degradation [78,79], benefiting from the inhere architecture [80] and based on the investigation on SCEs [81], indicated that still indomitable against SCEs even with a fairly thin SOI film [82]. Naturally, current into the substrate and gate-induced drain leakage (GIDL) current lessened [83,84] thanks to the carriers being strictly confined within the thin c Furthermore, with the implementation of back gate biasing, exc management was obtained [85,86], and electrostatic control represented a fast between off-state and on-state with decreased DIBL, SS, and variability.…”

Section: Fdsoi Salient Characteristicsmentioning

confidence: 99%

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CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Radamson,

Miao,

Zhou

et al. 2024

Nanomaterials

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After more than five decades, Moore’s Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures.

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Section: Fdsoi Salient Characteristicsmentioning

confidence: 99%

Section: Fdsoi Salient Characteristicsmentioning

confidence: 99%

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Radamson,

Miao,

Zhou

et al. 2024

Nanomaterials

View full text Add to dashboard Cite

show abstract

“…19,20 Unfortunately, it suffers from inhomogeneous strain profiles. 21,22 Alternatively, the use of micromechanical-or piezo-actuators can produce very homogeneous strain profiles but they suffer from the requirement of additional processing due to the requirement for electrical contacting. [23][24][25] Conceptually different is a technique introduced first in Si by Minamisawa et al 26 and later in Ge by Süess et al, 27 where strain is induced by a geometrical approach using patterning and underetching of layers with a positive pre-strain e 0 .…”

Section: Introductionmentioning

confidence: 99%