A review of the pseudo-MOS transistor in SOI wafers: operation, parameter extraction, and applications

“…These performance characteristics, while not optimized, are of the order expected for 0.145 m thick SOI bottom gate TFTs with channel lengths of this size using undoped source-drain contacts. 45 The combination of the DTL and RIE procedures described above also was found to be compatible with the PLs that are commonly used in commercial microelectronics fabrication processes. Multilayer lithography ͑i.e., bilayer and trilayer͒ methods have been developed by the microelectronics industry and provide critical process improvements that are required both to achieve higher resolution ͑e.g., by smoothing underlying substrate topography͒ and provide higher-aspect-ratio resist structures after etching.…”

Section: -3mentioning

confidence: 84%

Micron and submicron patterning of polydimethylsiloxane resists on electronic materials by decal transfer lithography and reactive ion-beam etching: Application to the fabrication of high-mobility, thin-film transistors

Ahn

Lee

Childs

et al. 2006

Journal of Applied Physics

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We describe a technique for fabricating micron and submicron-sized polydimethylsiloxane ͑PDMS͒ patterns on electronic material substrates using decal transfer lithography ͑DTL͒ in conjunction with reactive ion-beam etching ͑RIE͒. We validate the use of this unconventional polymeric system as a suitable resist material for fabricating Si-based microelectronic devices. In this process, an O 2 /CF 4 gas mixture was used to etch a supporting PDMS thin film that resides atop a closed-form decal polymer to reveal conventional resist structures. These structures provide an effective latent image that, in turn, provides for an extension of soft lithography as a form of multilayer lithography-one yielding submicron structures similar to those obtained from the conventional photochemical methods used to prepare such resists. This combined DTL/RIE patterning procedure was found to be compatible with commercially available planarization layers and provides a direct means for preparing high aspect ratio resist features. We illustrate the applicability of soft lithography as a means for fabricating electronic devices by using it to prepare model silicon-based thin-film transistors exploiting silicon-on-insulator wafer technology.

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“…To build up a reliable mass production technique, there is increasing demand for quick evaluation of the electrical properties of as-fabricated SOI wafers. The pseudo-MOSFET (W-MOSFET) technique, which was developed by Cristoloveanu et al [10], was proposed to characterize SOI wafers efficiently and rapidly [1,2]. It is the simplest kind of silicon-on-insulator (SOI) transistors and can be obtained on all SOI structure immediately.…”

Section: Introductionmentioning

confidence: 99%