A Review on Circuit Simulation Techniques of Single-Event Transients and their Propagation in Delay Locked Loop

Pasupathy, K. R.; Bindu, B.

doi:10.1080/02564602.2016.1184106

Cited by 15 publications

(3 citation statements)

References 18 publications

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“…However, its replication can be complex since the methodology does not depend only on device-level simulations. If the reader is interested in a more in-depth review of the modeling of SET, the authors refer the reader to the works of Pasupathy et al [10] and Andjelkovic et al [11].…”

Section: B Set Electrical Modelingmentioning

confidence: 99%

Single Event Transient on Combinational Logic: An Introduction and their Mitigation

Kessler

Ferraz

Rosa

et al. 2022

JICS

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Single event transients pose a major threat to the reliability of modern VLSI designs. Improving the robustness of combinational logic is challenging due to its complexity, masking effects, and signal dependence. This paper presents the mechanisms and concepts of SET generation, modeling, masking, and propagation in combinational logic. It also discusses design parameters and their impact on circuit robustness. An overview of automated design strategies for radiation hardening by design and their advantages and disadvantages is provided, covering gate sizing, gate duplication, gate remapping, load increase, layout spacing, and charge sharing techniques.

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Section: B Set Electrical Modelingmentioning

confidence: 99%

Single Event Transient on Combinational Logic: An Introduction and their Mitigation

Kessler

Ferraz

Rosa

et al. 2022

JICS

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“…This is because the connected current source is independent of its terminal voltage. This problem can be overcome by using switch‐and‐resistor technique [15, 16] to emulate the SET spike. Since there is a resistor that connects the output to ground, the output voltage does not go below ground rails.…”

Section: Circuit Simulation Of Setsmentioning

confidence: 99%

“…For LET

60 MeV normalc m^{2} / mg

, the pulse width‐and‐peak current thus obtained to be 97.7 ps and 3.87 mA, respectively. The switch‐and‐resistor technique is implemented using ohm's law in Verilog‐A to emulate the SET current, wherein the resistance is varied according to the shape of the current pulse [16]. The SET current pulse has three regions: a peak, a plateau and a tail‐like portion.…”

Section: Circuit Simulation Of Setsmentioning

confidence: 99%

Widening and narrowing of time interval due to single‐event transients in 45 nm vernier‐type TDC

Pasupathy

Bindu

2017

IET Circuits, Devices & Syst

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Single-event transients (SETs) due to heavy-ion (HI) strikes adversely affect the electronic circuits in sub-100 nm regime in radiation environment. Time-to-digital converter (TDC) is an important electronic component in many fields such as space applications and is used for measuring time precisely as a digital value. In this study, the effect of SET due to radiation strike on 45 nm vernier-type TDC with a resolution of 7 ps is analysed using cadence spectre circuit simulator. When HI strikes the delay line of TDC close to the START/STOP pulse transition, it either widens or narrows the time interval to be measured, depending on whether it strikes the top/bottom voltage-controlled delay line (VCDL). Results show that the TDC is sensitive if the SET occurs during the transition of START/STOP pulse. Moreover, the change in the time interval occurs in a regular staircase pattern, if the VCDL is struck at all instants near the pulse transition. These errors lead to erroneous digital output and cause abrupt deviations in the staircase transfer characteristics of TDC. SETs in other constituent components of TDC such as D-flip-flop and priority encoder produces glitches which can be mitigated using existing guard gate technique.

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Design and Optimization of Double-Gate MOSFET to Reduce the Effects of Single Event Transients

Aneesh

Pasupathy

Bindu

2019

Springer Proceedings in Physics

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A Review on Circuit Simulation Techniques of Single-Event Transients and their Propagation in Delay Locked Loop

Cited by 15 publications

References 18 publications

Single Event Transient on Combinational Logic: An Introduction and their Mitigation

Single Event Transient on Combinational Logic: An Introduction and their Mitigation

Widening and narrowing of time interval due to single‐event transients in 45 nm vernier‐type TDC

Design and Optimization of Double-Gate MOSFET to Reduce the Effects of Single Event Transients

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