A Review on Evaluation and Configuration of Fault Injection Attack Instruments to Design Attack Resistant MCU-Based IoT Applications

Abstract

The Internet-of-Things (IoT) has gained significant importance in all aspects of daily life, and there are many areas of application for it. Despite the rate of expansion and the development of infrastructure, such systems also bring new concerns and challenges. Security and privacy are at the top of the list and must be carefully considered by designers and manufacturers. Not only do the devices need to be protected against software and network-based attacks, but proper attention must also be paid to recently emerging hardware-based attacks. However, low-cost unit software developers are not always sufficiently aware of existing vulnerabilities due to these kinds of attacks. To tackle the issue, various platforms are proposed to enable rapid and easy evaluation against physical attacks. Fault attacks are the noticeable type of physical attacks, in which the normal and secure behavior of the targeted devices is liable to be jeopardized. Indeed, such attacks can cause serious malfunctions in the underlying applications. Various studies have been conducted in other research works related to the different aspects of fault injection. Two of the primary means of fault attacks are clock and voltage fault injection. These attacks can be performed with a moderate level of knowledge, utilizing low-cost facilities to target IoT systems. In this paper, we explore the main parameters of the clock and voltage fault generators. This can help hardware security specialists to develop an open-source platform and to evaluate their design against such attacks. The principal concepts of both methods are studied for this purpose. Thereafter, we conclude our paper with the need for such an evaluation platform in the design and production cycle of embedded systems and IoT devices.

A Systematic Review of Fault Injection Attacks on IoT Systems

“…This section analyzes other surveys in the literature that address fault injection attacks on IoT systems and devices to determine their shortcomings and justify the need for this systematic literature review. Kazemi et al [19] reviewed methods proposed in the literature that utilize clock and voltage fault generators to physically replicate fault injection attacks on the hardware devices of microcontroller based IoT systems. Their review article only considered hardware design validation methods against clock and voltage fault injection attacks, and focused on the methods for hardware security domain with primary studies solely from the perspective of microcontroller-based IoT applications.…”

“…The literature surveys presented in [1,19,20,25] analyzed the various hardware attack vectors to identify existing hardware vulnerabilities in components such as the microcontroller, clock generator, and voltage supply in the IoT system or device. The purpose of these surveys was to inform IoT hardware designers of the threats posed by fault injection attacks.…”

“…The physical level attack detection methods described in Section 5.2.1 [3,5,19,29,32,38,42] all require a separate physical hardware monitoring setup alongside the target IoT system or device to detect fault injection attacks. This makes such attack detection methods expensive, and the hardware monitoring setup needs to be adjusted for every IoT application.…”

Evaluation of IoT Self-healing Mechanisms using Fault-Injection in Message Brokers

“…Although most literature regarding IoT and fault-injection focuses on hardware faults via physical interaction with devices [25,29,46] rather than interfering with the application layer logic (including communication channels and middleware components), the usage of software techniques to exercise in-place fault-tolerance mechanisms can be traced to as early as 1993 [5]. More recently, particularly in cloud computing, Chaos Engineering became an umbrella term to techniques that inject, observe and collect information concerning the impact of faults on a running system [8,11,41].…”

Low-Cost Soft Error Robust Hardened D-Latch for CMOS Technology Circuit

“…Thus, nano-scale CMOS circuits are more vulnerable to errors, such as the Soft Error (SE) caused by Single Event Upset (SEU) [1]. These errors have a huge negative impact on hardware security of integrated circuits, which is invested frequently [2,3], even for electronic applications [4][5][6]. In the particular case of SE, they have to be addressed as a hardware security or hardware reliability issue since they can be caused by and from the environment.…”