A review on regular clocking scheme in quantum dot cellular automata

Goswami, Mrinal; Sharma, Tonmoy Jyoti; Boruah, Arpita Nath

doi:10.1016/j.prime.2024.100588

e-Prime - Advances in Electrical Engineering, Electronics and E

2024

DOI: 10.1016/j.prime.2024.100588

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A review on regular clocking scheme in quantum dot cellular automata

Mrinal Goswami,

Tonmoy Jyoti Sharma,

Arpita Nath Boruah

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2024

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Cited by 2 publications

References 15 publications

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A novel SRAM with SET and RESET functions using a novel 5-input majority gate in quantum-dot cellular automata (QCA) technology

Rathore,

Singh

2024

Phys. Scr.

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In the nanoscale VLSI industry, Quantum-dot Cellular Automata (QCA) presents a novel substitute for conventional Complementary Metal-Oxide-Semiconductor (CMOS) technology. This paper introduces a new design that uses QCA technology. The design includes a 5-input Majority Gate (5-MG), a fundamental component in QCA, and a Static Random Access Memory (SRAM) cell with set and reset features. The recommended design offers a minimum clock cycle, a small QCA layout area, less cost function, and a sustainable arrangement to get the ideal size and latency while consuming less power. The proposed 5-input majority gate (MG) has a total area of 0.009 µm2 and a QCA cell count of 14. Further, a novel SRAM cell is implemented using the 5-input MG logic. The SRAM cell designed using 44 QCA cells has a clock latency of 1 and a layout area of 0.03 µm2. Compared to the conventional 5-MG SRAM cell the proposed 5-MG SRAM cell shows a 50% reduction in cell counts and a 62.5% reduction in total layout area.

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A novel SRAM with SET and RESET functions using a novel 5-input majority gate in quantum-dot cellular automata (QCA) technology

Rathore,

Singh

2024

Phys. Scr.

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Efficient adders for nano computing: an approach using QCA

Qureshi,

Khan,

Arya

2024

Phys. Scr.

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This research paper presents a detailed evaluation of Quantum-dot Cellular Automata (QCA) digital adder designs utilizing advanced analytical tools, specifically QCADesigner, QCAPro, and QCADesigner-E. The study introduces novel adder designs that significantly enhance cell efficiency, reduce latency, and optimize cost. The study underscores the benefits of using coplanar crossovers to reducefabrication complexity and avoid additional cell layers, which helps maintain high polarization levels and operational efficiency. The proposed full adder, built using a three-input XOR gate, shows a significant 88% reduction in QCA-specific cost (QSC) and a 0.5 clock cycle reduction in latency compared to the bestoptimized existing designs. This improvement is achieved by integrating a single majority gate and MMV gate, removing the need for inverters and consuming 144.2 meV of energy. This design offers a majorenhancement over previous designs, which lack such thorough evaluations. Additionally, the proposed ripple carry adder uses 40 fewer cells, achieves a 0.75 clock cycle reduction in latency over the best available design, provides an 81% improvement in QSC, and demonstrates a fully scalable and reliable circuit suitable for nanocomputing applications. Furthermore, the study introduces a single-bit carry look-ahead adder based on half-adder instantiation, with the proposed four-bit carry look-ahead adder achieving a 14% improvement in QCA-specific cost, highlighting its innovative features and practical advantages for advanced QCA circuits.

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A review on regular clocking scheme in quantum dot cellular automata

Cited by 2 publications

References 15 publications

A novel SRAM with SET and RESET functions using a novel 5-input majority gate in quantum-dot cellular automata (QCA) technology

A novel SRAM with SET and RESET functions using a novel 5-input majority gate in quantum-dot cellular automata (QCA) technology

Efficient adders for nano computing: an approach using QCA

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