A review on various multipliers designs in VLSI

Singh, Khuraijam Nelson; Tarunkumar, Huirem

doi:10.1109/indicon.2015.7443420

Cited by 15 publications

(3 citation statements)

References 27 publications

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“…This multiplier uses the common add and shift method to achieve multiplication. [13] The multiplicand is multiplied by each bit of the multiplier to get the partial product. After that, the partial product is relocated by its bit order before being appended at the very end.…”

Section: G Array Multipliermentioning

confidence: 99%

Energy-Efficient Approximate Multiplier with Flexible Precision

Vinodia

2024

IJRASET

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The method that can be utilized to increase accuracy and decrease energy use is approximate multiplication. A key component of many error-tolerant applications is multiplication. Approximate multipliers are increasingly utilized in energyefficient computing for applications tolerant of inaccuracy. Apart from multiplier performance, determining the appropriate approximate multiplier is challenging due to considerations of area and delay. Therefore, selecting the type of approximate full adder (FA) becomes a crucial decision-making factor. These adders are employed for summing partial products in multipliers. This study presents the design and evaluation of an approximate multiplier employing four distinct approximate adders. The design undergoes simulation and synthesis using Xilinx and Model Sim. Compared to previously proposed approximate multipliers, the proposed circuits demonstrate substantial reductions in area, time delay, and power consumption. According to experimental data, the area, latency, and average power consumption of the suggested adjustable approximate multiplier can be lowered by 10%, 34.96 ns, and 300 mW when contrasted to the Wallace tree multiplier.

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Section: G Array Multipliermentioning

confidence: 99%

Energy-Efficient Approximate Multiplier with Flexible Precision

Vinodia

2024

IJRASET

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“…The multiplier takes up the majority of the space in any digital circuit. If a properly optimized multiplier is not used, it will generate lag [4]. Area, total power dissipation, and propagation latency are the most significant elements to consider when evaluating the performance of a system.…”

Section: Introductionmentioning

confidence: 99%

“…In [3] it is revealed that a multiplexer-based array multiplier outperforms a modified Booth multiplier in terms of speed and power dissipation by 13 to 26 percentage due to lower internal capacitance and how area-efficient complete adder circuits (SERF and 1OT 1111) can assist reduce overall routing capacitance, leading in lower power consumption for multipliers based on these adder circuit. In [4] it introduces a new multiplexer-based truncated array multiplier that takes advantage of three existing truncation techniques and improves them. To analyse the truncation errors of the new truncated multiplier, an extensive error analysis was undertaken.…”

Section: Introductionmentioning

confidence: 99%

Area Efficient Modified Array Multiplier

Shetty¹,

Kiran²

2021

JUSST

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Multipliers are widely used for various application like signal processing. Multipliers are used for multiplication two binary data .There are different kinds of multipliers with their own advantages and disadvantages. In this paper we implemented Array multiplier which has considerably more speed but also more area, it was implemented using pseudo NMOS logic in Cadence software and the number of transistors was reduced from 2N to N+1 which also lead to reduction in area.

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