A revised version of the ATLAS Tile Calorimeter link Daughterboard for the HL-LHC

Abstract

The ATLAS Tile Calorimeter (TileCal) readout link and control daughterboard (DB) is the central on-detector hub of the new TileCal electronics upgrade for the high-luminosity large hadron collider (HL-LHC). The DB, which has undergone gradual redesigns during development, provides the connection between the on-and off-detector electronics via bidirectional fiber-optic links. Two CERN-developed, radiation hard GBTx application specified integrated circuits (ASICs) receive LHC timing signals and configuration commands through 4.8-Gb/s downlinks, which are in turn propagated to the front end through Xilinx Kintex Ultrascale field-programmable gate arrays (FPGAs). The Kintex FPGAs also continuously perform real-time readout and transmission of digitized photomultiplier (PMT) samples, detector control system (DCS) signals, and monitoring data through redundant pairs of 9.6-Gb/s uplinks. The DB design aims at minimizing single points of failure and improving the performance and reliability of the board. Apart from the GBTx devices, the DB design relies on radiation-qualified commercial off-the-shelf (COTS) components. Mitigation of radiationinduced single-event upsets (SEUs) in the FPGAs is performed by a combination of the Xilinx soft error mitigation (SEM) controller and triple-mode redundancy (TMR) schemes in the FPGA firmware. Data integrity is protected through forward error correction (FEC) in the downlinks and cyclic redundancy check (CRC) error verification in the redundant uplinks. This article presents the latest revision of the DB (version 6), a redesign that addresses single-event latch-up (SEL) behavior observed in the Kintex Ultrascale+ FPGAs used in the previous revision, and features a more robust power circuitry combined with an improved current monitoring scheme, enhanced performance of the analog-to-digital converter (ADC) read-out, and improved timing performance.

Radiation studies performed on the High Luminosity ATLAS TileCal link Daughterboard

“…None of the components were damaged by the deposited TID: DB6-1 and DB6-2 were irradiated with Gamma radiation at 60 Co at the CERN CC60 facilities to 220 Gy at a rate of 3.37 Gy/h (figure 9 of ref. [11]) and up to 54 Gy at a rate of 0.33 Gy/h (figure 10 of ref. [11]), respectively.…”

“…[11]) and up to 54 Gy at a rate of 0.33 Gy/h (figure 10 of ref. [11]), respectively. DB6-1 ran stable during the full test, however it showed an increase in the current measured in the 0.95 V power line of both sides of the board of at around 140 Gy.…”

“…For the Single Event Latchups (SEL) tests, there was no prototype of the DB produced and the design was migrating from the 16 nm FinFET powered KU+ FPGA to the KU FPGA, due to the KU+ alternative been susceptible to SEL occurrences. As an alternative to the ProASIC, a Lattice ICE40LP FPGA was also tested [11]. Two separate tests were performed for SEL, one as described for the DB6-3 with 54 MeV protons, where the FPGAs were irradiated to a fluence of 2.62 × 10 11 p/cm 2 .…”

“…In the second test, two Trenz TE0841 boards (each with the same KU FPGA used in the DB design), a Lattice ICE40LP FPGA and a ProASIC3E A3P31500 FPGA were irradiated with 226 MeV protons to a fluence of 1.11 × 10 12 p/cm 2 , for which all the currents of the FPGAs were monitored (figure 6 of ref. [11]). No SEL were observed in the units under test in either of the tests.…”