A Robust and Efficient Method For Error Detection And Correction In Memories

Abstract

Due to higher integration densities, technology scaling and variation in parameters, the performance failures may occur for every application. The memory applications are also prone to single event upsets and transient errors which may lead to malfunctions. The paper deals with the idea of a novel fault detection and correction technique using EG-LDPC codes with the application mainly focused on memories. The majority logic decoding is used here, since it can correct a large number of errors. Even though the majority decoding consumes more time, it can be overcome by the proposed technique which detects the errors in less cycle time. It can obviously reduce memory access time when the data read process is error free. The use of an additional logic results in a slight area overhead in proposed method when compared to the existing technique, which is overcome by a modified implementation of majority gate. The results obtained are compared with the existing version of the technique.