A robust cell-level crosstalk delay change analysis

Keller, Igor; Tseng, K.; Verghese, Nishath K.

doi:10.1109/iccad.2004.1382562

Cited by 77 publications

(64 citation statements)

References 8 publications

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“…We are aware that such a model is an abstraction of more complex simulation-based models [13], [7] but algorithmic contributions presented in this paper are orthogonal to model choice as long as the model is slew and alignment based. Our goal is to use a fast evaluation model that has high fidelity in order to drive the algorithm in the right direction as the model is evaluated many times in our algorithm.…”

Section: Coupling Modelmentioning

confidence: 99%

Pessimism Reduction in Coupling-Aware Static Timing Analysis Using Timing and Logic Filtering

Das

Killpack

Kashyap

et al. 2010

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-With continued scaling of technology into nanometer regimes, the impact of coupling induced delay variations is significant. While several coupling-aware static timers have been proposed, the results are often pessimistic with many false failures. We present an integrated iterative timing filtering and logic filtering based approach to reduce pessimism. We use a realistic coupling model based on arrival times and slews and show that non-iterative pessimism reduction algorithms proposed in previous research may give potentially nonconservative timing results. On a functional block from an industrial 65nm microprocessor, our algorithm produced a maximum pessimism reduction of 11.18% of cycle time over converged timing filtering analysis that does not consider logic constraints.

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Section: Coupling Modelmentioning

confidence: 99%

Pessimism Reduction in Coupling-Aware Static Timing Analysis Using Timing and Logic Filtering

Das

Killpack

Kashyap

et al. 2010

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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show abstract

“…Note that i L is the admittance function of the load multiplied by the output voltage. In [9] it is shown how to use the Pade method to approximate the admittance function of an RC network with a reduced order representation. As reported in [9] in most cases only one Pade term ( i.e., Π model approximation) is sufficient for the error to be within 2-3% of Spice and in a few cases where one pole is not sufficient, more Pade terms should be preserved.…”

Section: B Output Voltage Calculationmentioning

confidence: 99%

“…As before, a Pade approximation [9] is used to model the load and substitute i L-Q (i L-Q_bar ) as a function of the output voltage V Q (V Q_bar .) An Euler integration method is used to numerically solve the two unknown voltages V Q and V Q_bar from Equations (12) Solving Equations (12) and (13) when there is no feedback for the sequential cell (i.e., CLK=1, CLK_bar=0, and so I Q ≈0), is similar to calculating the output voltage of an inverter for which the input comes from a transmission gate.…”

Section: E Output Voltage Calculationmentioning

confidence: 99%

“…Close-to-SPICE accuracy with orders of magnitude faster than SPICE tools, make the CSM-based analysis very attractive. For example in [9] an efficient CS-based technique for worst case aggressor alignment is described that can reduce the pessimism of the conventional voltage based techniques by 50%.…”

Section: Introductionmentioning

confidence: 99%

“…In [8], a Blade-based model is used and the input and output voltage waveforms are approximated with Weibull functions. Keller et al [9] presented a CS model for the purpose of crosstalk noise analysis. Similar to Blade, a pre-characterized current source is used.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Accurate Timing and Noise Analysis of Combinational and Sequential Logic Cells Using Current Source Modeling

Nazarian

Fatemi

Pedram

2011

IEEE Trans. VLSI Syst.

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Library Compatible Variational Delay Computation

Silva

Zhu

Phillips

et al.

IFIP International Federation for Information Processing

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With technology steadily progressing into nanometer dimensions, precise control over all aspects of the fabrication process becomes an area of increasing concern. Process variations have immediate impact on circuit performance and behavior and standard design and signoff methodologies have to account for such variability. In this context, timing verification, already a challenging task due to the sheer complexity of todays designs, becomes an increasingly difficult problem. Statistical static timing analysis has been proposed as a solution to this problem, but most of the work has focused in the development of timing engines for computing delay propagation. Such tools rely on the availability of delay formulas accounting for both cell and interconnect delay that take into account unpredictable variability effects. In this paper, we concentrate on the impact of interconnect on delay and propose an extension to the standard modeling strategies that is variation-aware and compatible with such statistical engines. Our approach, based on a specific type of perturbation analysis, allows for the analytical computation of the quantities needed for statistical delay propagation. We also show how perturbation analysis can be performed when only the standard delay table lookup models are available for the standard cells. This makes the proposed approach compatible with existing timing analysis frameworks. Results from applying our proposed modeling strategy to computing delays and slews in several instances accurately match similar results obtained using electrical level simulation.

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A robust cell-level crosstalk delay change analysis

Cited by 77 publications

References 8 publications

Pessimism Reduction in Coupling-Aware Static Timing Analysis Using Timing and Logic Filtering

Pessimism Reduction in Coupling-Aware Static Timing Analysis Using Timing and Logic Filtering

Accurate Timing and Noise Analysis of Combinational and Sequential Logic Cells Using Current Source Modeling

Library Compatible Variational Delay Computation

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