A Robust Chaos-Based True Random Number Generator Embedded in Reconfigurable Switched-Capacitor Hardware

Drutarovský, Miloš; Galajda, Pavol

doi:10.1109/radioelek.2007.371423

Cited by 72 publications

(55 citation statements)

References 10 publications

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“…This is the case of generators using analog components like analog amplifiers [12] or analog to digital converters used in chaos-based TRNGs [13], [14]. Furthermore, some digital designs require full custom digital technology and are thus not feasible in FPGAs [15], [16].…”

Section: Selection Of Trng Coresmentioning

confidence: 99%

A survey of AIS-20/31 compliant TRNG cores suitable for FPGA devices

Petura

Mureddu

Bochard

et al. 2016

2016 26th International Conference on Field Programmable Logic and Applications (FPL)

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Abstract-FPGAs are widely used to integrate cryptographic primitives, algorithms, and protocols in cryptographic systemson-chip (CrySoC). As a building block of CrySoCs, True Random Number Generators (TRNGs) exploit analog noise sources in electronic devices to generate confidential keys, initialization vectors, challenges, nonces, and random masks in cryptographic protocols. TRNGs aimed at cryptographic applications must fulfill the security requirements defined in the German Federal Bureau for Information Security's (BSI) recommendations AIS-20/31, which has become a de facto standard in Europe. Many TRNG cores have already been published, only a few of which are suitable for FPGAs and even fewer comply with AIS-20/31. Here we present the results of the implementation of AIS-20/31 compliant TRNG cores in three FPGA families: Xilinx Spartan 6, Altera Cyclone V and Microsemi SmartFusion 2. In addition to common design parameters like area, bit rate and power/energy consumption, we compare and discuss the feasibility of generator cores in different FPGAs and the statistical quality of their output. These results will help designers select the best generator and the device family to match the requirements of the data security application. To ensure reproducibility of the results, the open source VHDL code of all generators adapted to individual families can be downloaded from the dedicated web page.

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Section: Selection Of Trng Coresmentioning

confidence: 99%

A survey of AIS-20/31 compliant TRNG cores suitable for FPGA devices

Petura

Mureddu

Bochard

et al. 2016

2016 26th International Conference on Field Programmable Logic and Applications (FPL)

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show abstract

“…Due to their structural stability, one expects systems with hyperbolic attractors to be of particular interest as generators of robust chaos for electronic communication systems, random number generators, and various forms of encryption schemes [30][31][32].…”

Section: Introductionmentioning

confidence: 99%

Hyperbolic chaotic attractor in amplitude dynamics of coupled self-oscillators with periodic parameter modulation

2011

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“…Another researcher [113] used logistic map like chaos-based true random number generator embedded in reconfigurable switchedcapacitor hardware. Another paper [85] proposed an algorithm of generating pseudorandom number generator, which was called remember CML -couple map lattice based on discrete chaotic iteration and combined the couple map lattice and chaotic iteration Q7…”

Section: Algorithm Dynamics Powered By Deterministic Chaosmentioning

confidence: 99%