A robust constraint solving framework for multiple constraint sets in constrained random verification

Abstract

To verify system-wide properties on SoC designs in Constrained Random Verification (CRV), the default set of constraints to generate patterns could be overridden frequently through the complex testbench. It usually results in the degradation of pattern generation speed because of low hit-rate problems. In this paper, we propose a technique to preprocess the solution space under each constraint set. Regarding the similarity between constraint sets, the infeasible subspaces under a constraint set help identify the infeasible subspaces under another constraint set. The profiled results under each constraint set are then stored in a distinct range-splitting tree (RS-Tree). These trees accelerate pattern generation under multiple constraint sets and, simultaneously, ensure the produced patterns are evenly-distributed. In our experiments, our framework achieved 10X faster pattern generation speed than a state-of-art tool in average.

A High Performance Advanced Encryption Standard (AES) Encrypted On-Chip Bus Architecture for Internet-of-Things (IoT) System-on-Chips (SoC)

“…Constraint-Random Verification: Constraint-random verification offers a highly effective way to deal with the challenges of SoC verification [33,170]. These challenges are overwhelming for many reasons: complex instruction sets, multiple pipeline stages, in-order or out-of-order execution strategies, instruction parallelism, fixedand floating-point scalar/vector operations, and other features that create a seemly never-ending list of corner cases to exercise.…”