A Robust SRAM Design for Ultra Dynamic Voltage Scalable VLSI System

Abstract

In this paper, a SRAM array targeting IBM 130nm CMOS technology is proposed for ultra dynamic voltage scaling (UDVS) application with better immunity against process variation. A type of modified Schmitt Trigger inverter is adopted in the SRAM design, which guarantee stable operations in both superthreshold and subthreshold supply voltage regions. Testing results demonstrate that the proposed SRAM array functions well in the supply voltage range of 150 mV to 1200 mV. The optimum-energy supply voltage point is about 400 mV for proposed UDVS SRAM array. And the energy at 400 mV decreases by 62.5% compared to that at 1200 mV.