A robust, ultra low-power, data-dependent-power-supplied 11T SRAM cell with expanded read/write stabilities for internet-of-things applications

Sharma, Vishal; Gopal, Maisagalla; Chouhan, Shailesh Singh

doi:10.1007/s10470-018-1286-2

Cited by 41 publications

(27 citation statements)

References 37 publications

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“…This improves the I on /I o f f ratio of the cell. The isolated read structure are also reported in PCF10T [18] and LP12T [19] as depicted in Fig.2(b) and Fig.2(c). During read activity, isolation structure between storage nodes and bit-lines prevent to flow read current through the storage nodes that eliminate the capacitive noise generated through bitlines which enhance read noise margin of cell.…”

Section: Introductionmentioning

confidence: 90%

“…The write power consumption at different supply voltages has seen in Fig.7 (c). It has indicated that the write power of the LP9T SRAM cell is decreased 2.1×,3.64×, 2.06×,1.96×,4.23×,2.45× as compared to Conv.6T [28],DF8T [21],TG8T [26],PCF10T [18],SPG11T [20],LP12T [19] SRAM cells respectively. This happens due to the weaken of pull-up path through PMOS (P1 and P2) transistors.…”

Section: Read/write Power Dissipationmentioning

confidence: 99%

“…Fig.8(a) shows the time of read access which considered SRAM topologies at various supply voltages value. It is noticed that the LP9T SRAM cell, read access time has been improved by 2.72×,2.5×,3.55×,8.15×,3.49×,5.56× as compared to Conv.6T [28],DF8T [21],TG8T [26],PCF10T [18], SPG11T [20],LP12T [19] SRAM cells respectively. It is attributed to the forward body bias technique in read path which reduces the threshold voltage of N5 transistor which takes minimum time to discharge the read bit-line.…”

Section: Read/write Access Timementioning

confidence: 99%

“…A voltage controlled method [25] is used to minimize the leakage and dynamic power with plenty of increased area of the SRAM cell. A data-dependent supply voltage technique in 11T SRAM cell is utilized to decreases power consumption of the cell [19]. Besides, transmission gate is used at storage node of TG8T SRAM cell as presented in Fig.2(f) to decreases write power consumption in the cell [26].…”

Section: Introductionmentioning

confidence: 99%

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A Low Leakage 9T SRAM Cell With Improve Stability in Sub-Threshold Region for IoT Applications

Kumar¹,

Tomar²

2021

Preprint

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This paper presents a single-ended read and differential write half select free 9T static random access memory (SRAM) cell operates in the sub-threshold region. Proposed 9T SRAM cell shows a reasonable reduction in read and write power dissipation by a factor of 1.41× and 2.1× respectively as of conventional 6T (Conv.6T) SRAM cell. The stacking of transistors at core latch network minimizes the leakage power of the cell. The read static noise margin (RSNM) and write margin (WM) are upgraded by 2.16× and 2.06× respectively as of Conv.6T cell. A forward body bias technique is utilized in read path which results to decreases in read access time by a factor of 2.72× as of standard 6T SRAM cell. The mean value of Ion/Ioff ratio of the proposed cell is improved by 2.92× as compared to the Conv.6T SRAM cell. It is attributed to a reduction in bit-line leakage current. To achieve more soundness in characteristics of the proposed 9T SRAM cell, process variation effect on RSNM, power dissipation, and read current is calculated through Monte Carlo (MC) simulation at 5000 points. The obtained results are compared with reference SRAM cells at 0.3V supply voltage.

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Section: Introductionmentioning

confidence: 90%

Section: Read/write Power Dissipationmentioning

confidence: 99%

Section: Read/write Access Timementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A Low Leakage 9T SRAM Cell With Improve Stability in Sub-Threshold Region for IoT Applications

Kumar¹,

Tomar²

2021

Preprint

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show abstract

“…Thus, the unselected cells get affected and chance to flip the stored data. Hence this issue is called column half‐select issue 30,31 . The conventional 6T cell faced that issue due to less number of control signals as shown in Figure 7A.…”

Section: Proposed D2lp10t Sram Cellmentioning

confidence: 99%

An energy‐efficient data‐dependent low‐power 10T SRAM cell design for LiFi enabled smart street lighting system application

Gupta

Sharma²,

Shah

et al. 2020

Int J Numerical Modelling

Self Cite

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The LiFi enabled smart street lighting system requires the adaptive SoC to save huge amount of power/energy for data storage, which plays an important role for any urban area development. For the above application, an energy-efficient data-dependent power supplied 10T SRAM cell with half-select free readdecoupled circuit is designed to boost stability while stacking effect controls the leakage current against the process-voltage-temperature variations. CMOS 65 nm technology node is used for the implementation and comparison of various SRAM cells. The proposed cell offers 4×, 1.15×, and 1.66× higher read, hold, and write stability, respectively, as compared with the 6T cell at 0.4 V supply voltage. The improvement of write, read, and leakage power of the proposed 10T cell are 98.03%, 56.25%, and 91.07%, respectively, as compared with the 6T cell at 0.2 V supply. It is also observed that the proposed 10T cell has 88.88% and 85.71% write 0 and write 1 energy, respectively, as compared with the 6T cell at 0.2 V supply voltage. To better assess the cell, we introduced the figure of merit (FOM) and observed that the FOM of the proposed cell is 125× higher as compared with the 6T cell at 0.4 V supply voltage.

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Single‐ended half‐select disturb‐free 11T static random access memory cell for reliable and low power applications

Abbasian

Gholipour

2021

Circuit Theory & Apps

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Summary This paper presents an 11 transistor (SEHF11T) static random access memory (SRAM) cell with high read static noise margin (RSNM) and write static noise margin (WSNM). It eliminates the write half‐select disturb using cross‐point data‐aware write word lines, which can mitigate bit‐interleaving structure to reduce multiple‐bit upset and increase soft‐error immunity. We evaluated and analyzed the effect of process, voltage, and temperature (PVT) variations on various design metrics and compared it with other cells. The SEHF11T performs fast read operation due to its higher read current and slow write operation due to its single‐ended nature. It employs the read decoupling technique to enhance the RSNM. The stacked transistors in the left/right half‐cell increase the RSNM. In addition, the WSNM is improved by eliminating the feedback of cross‐coupled inverters pair during write operation by means of power‐cutoff write‐assist technique. The proposed cell shows 1.11X higher RSNM and 1.37X higher WSNM compared to fully differential 8T (FD8T) cell. The stacked transistors in the cell reduce leakage power dissipation. The SEHF11T consumes 0.47X lower leakage power compared to FD8T at VDD = 0.7 V. Furthermore, it exhibits high reliability against PVT variations in subthreshold region and shows 1.09X narrower spread in leakage power than that of FD8T at VDD = 0.3 V.

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A robust, ultra low-power, data-dependent-power-supplied 11T SRAM cell with expanded read/write stabilities for internet-of-things applications

Cited by 41 publications

References 37 publications

A Low Leakage 9T SRAM Cell With Improve Stability in Sub-Threshold Region for IoT Applications

A Low Leakage 9T SRAM Cell With Improve Stability in Sub-Threshold Region for IoT Applications

An energy‐efficient data‐dependent low‐power 10T SRAM cell design for LiFi enabled smart street lighting system application

Single‐ended half‐select disturb‐free 11T static random access memory cell for reliable and low power applications

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