A rule-based circuit representation for automated CMOS design and verification

Wu, Chih-Feng; Wojcik, A.S.; Ni, Lionel M.

doi:10.1145/37888.38012

Cited by 7 publications

(1 citation statement)

References 15 publications

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“…the problems of VLSI/CAD have been focused on verification [23], synthesis [6], placement [16], routing [5,12], layout generation [13][14][15], and even on an application specific integrated circuit (ASIQ design [21] _ To ^ authors , _ knowledge( there has been no publication in any journal for knowledge-based expert system in layout compaction until now [9]. Since manual compaction is tedious, time-consuming, and error-prone, many traditional algorithmic approaches [7,20] have been proposed in the past decades.…”

Section: Introductionmentioning

confidence: 99%

An application of an expert system in layout compaction of VLSI design

Hsiao

Feng

Chen

1989

Journal of the Chinese Institute of Engineers

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Recent research in knowledge-based expert systems of VLSI design tools has concentrated on placement, routing, and cell generation. This paper presents an alternative application for artificial intelligence (AI) techniques on compaction design for a VLSI mask layoutexpert compactor. In order to overcome the shortcomings of iterative search through a large problem space within a working memory, and therefore, to speed-up the runtime of compaction, a set of rule-based region query operations and knowledge-based techniques for the plane sweep method are proposed in this system. Experimental results have explored the possibility of using expert system technology (EST) to automate the compaction process by "reasoning" out the layout design and applying sophisticated expert rules to its knowledge base.

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