A run-time RTL debugging methodology for FPGA-based co-simulation

Cheng, Xiaoshu; Ruan, Anbang; Liao, Yulong; Li, P.; Huang, Haocheng

doi:10.1109/icccas.2010.5581847

Cited by 11 publications

(6 citation statements)

References 12 publications

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“…Through experimentation, it was observed that existing approaches lack internal debug capabilities that our solution can provide in order to debug video applications. In comparison with other works [18,19,24], we also provide additional capabilities. We introduce test signals within the double transceiver architecture (to encode/decode video stream) making our solution capable of analyzing a complete solution.…”

Section: Discussionmentioning

confidence: 99%

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A novel FPGA-based test-bench framework for SDI stream verification

Conti

Kyrkou

Theocharides

et al. 2020

J Image Video Proc.

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This paper presents a framework for complete simulation and verification of Serial Digital Interface (SDI) video using a verilog test-bench and geared toward FPGAs. This framework permits simulating the entire process: from test video signal generation to protocol verification in the FPGA which implements the Device Under Test (DUT). The novelty in the design is the combination of a customized test video signal generator with an implementation clone of DUT transceiver for in-depth protocol debugging. Identical input test patterns of the video protocol under test are generated and fed to DUT for verification. Thus, the model not only permits to evaluate the SDI transport layer but also validates the implementation at ultra low pixel level of the video format. This approach provides two advantages: cost saving in terms of additional lab test equipment and delivering all-in-one test solution to verify design and implementation. A practical implementation using a test example of a macroblock processing chain using SDI video interface shows the viability of the proposed framework for video protocol testing.

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Section: Discussionmentioning

confidence: 99%

“…Another approach to tackle this problem is proposed in [19]. The verification method compiles the test-bench on a computer.…”

Section: Background and Related Workmentioning

confidence: 99%

A novel FPGA-based test-bench framework for SDI stream verification

Conti

Kyrkou

Theocharides

et al. 2020

J Image Video Proc.

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“…It took 55.81 s to monitor the entire validation at a minimum amount of BRAMs and it generated a VCD file with a size of 434 MB. In future works, this monitoring implementation can be improved with a scan-chain methodology presented in [20] or statistical sampling method [21].…”

Section: Resultsmentioning

confidence: 99%

Hybrid Prototyping Methodology for Rapid System Validation in HW/SW Co-Design

Wicaksana

Charif

Andriamisaina

et al. 2019

2019 Conference on Design and Architectures for Signal and Image Processing (DASIP)

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As the System-on-Chip (SoC) complexity increases, hardware/software co-design plays an important role to improve design productivity, reduce time to market, and optimize the overall results. Consequently, there is a high interest in providing rapid system validation in such a paradigm to achieve the aforementioned objectives. There exist in previous works prototyping techniques related to the development phase. FPGA-based prototyping has the benefits of enabling HW/SW integration and system validation after the Register Transfer Level (RTL) implementation is available while virtual platforms provide capabilities to accelerate software development with higher level functional models, e.g. Transaction Level Modeling (TLM). In this paper, we propose a hybrid prototyping methodology which takes advantage of virtual and FPGA-based prototyping in a single framework. We aim to provide a rapid and flexible system validation solution for HW/SW co-design at various stages of development based on the availability of TLM and RTL implementations. The proposed methodology allows online and offline performance analysis and debugging for early feedback in HW/SW architecture exploration. This was evaluated in the experiments with a neural network processor as a case study.

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“…Our system expects this specification only at block level, which is much easier owing to a designer's block level view of a SoC design. Co-simulation based RTL debug systems have been studied in [11,12]. In both cases, testbench resides on HDL simulator and the DUT runs on FPGA based emulator, while observability of internal nodes of DUT is provided via interface calls of HDL simulator.…”

Section: Previous Workmentioning

confidence: 99%

“…In both cases, testbench resides on HDL simulator and the DUT runs on FPGA based emulator, while observability of internal nodes of DUT is provided via interface calls of HDL simulator. In [11], internal node probing in FPGA is achieved by connecting DUT signals to a PCI-extended bus, and in [12] the same is achieved by insertion of scan chains in design. Both the systems have substantial area overhead that reduces effective capacity of the emulator.…”

Section: Previous Workmentioning

confidence: 99%

Fast and scalable hybrid functional verification and debug with dynamically reconfigurable co-simulation

Banerjee¹,

Gupta²

2012

Proceedings of the International Conference on Computer-Aided Design

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Hybrid functional verification and debug systems which combine high execution speed of logic emulators and full observability and controllability of software simulators are widely used, but suffer from scalability problem since software simulators cannot handle large and complex System-on-chip (SoC) designs efficiently, restricting their application to only relatively small designs. This paper presents a completely scalable hybrid verification and debug system based on dynamically reconfigurable co-simulation. Unlike existing systems, it allows one or more component logic blocks of a SoC to run on simulator for debugging while rest of the design still runs on emulator. The full design under test (DUT) is run on emulator at near hardware speed for long test sequences, and on error detection one or more logic blocks are transparently switched over to simulation for debugging, initializing the system as a piecewise cosimulator. Logic blocks can be flexibly relocated between simulator and emulator dynamically, without going through time consuming design recompilation phase, allowing designers to quickly debug functional issues. Application of the system to verification of real complex designs shows the effectiveness of our approach.

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A run-time RTL debugging methodology for FPGA-based co-simulation

Cited by 11 publications

References 12 publications

A novel FPGA-based test-bench framework for SDI stream verification

A novel FPGA-based test-bench framework for SDI stream verification

Hybrid Prototyping Methodology for Rapid System Validation in HW/SW Co-Design

Fast and scalable hybrid functional verification and debug with dynamically reconfigurable co-simulation

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