A Runtime Programmable Accelerator for Convolutional and Multilayer Perceptron Neural Networks on FPGA

Kabir, Ehsan; Poudel, Arpan; Aklah, Zeyad; Huang, Miaoqing; Andrews, Davıd L.

doi:10.1007/978-3-031-19983-7_3

Cited by 2 publications

(3 citation statements)

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“…Inference time comparison of SPLVP with respect to CNN-MLPA in [71] when synthesized for MLP operations, and for different number of PEs.…”

Section: Tablementioning

confidence: 99%

“…Tab. 7 compares the inference time of SPLVP with the programmable CNN-MLP Accelerator (CNN-MLPA) in [71], which can be synthesized using Xilinx Vivado High-Level Synthesis (HLS) to support MLP operations in floating point format (with selectable precision). The system runs at 100 MHz and each PE comprises similar sub-blocks as in MLPCP [38].…”

Section: Tablementioning

confidence: 99%

“…7, requires 18218 LUTs, 6 DSPs, 11670 registers, and 222 BRAMs, for an estimated OD of 6•10 −3 , where the number of operations has been calculated as throughput divided by the clock frequency reported in Tab. 4 in [71]. SPLVP provides the lowest resource usage.…”

Section: Tablementioning

confidence: 99%

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An 8-bit Single Perceptron Processing Unit for Tiny Machine Learning Applications

Crepaldi,

Salvo,

Merello

2023

IEEE Access

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We present a tiny MultiLayer Perceptron (MLP) accelerator named Single Perceptron Linear Vector Processor (SPLVP) that aims at extending the capabilities of limited resources MCUs, enabling inference time speedup and main CPU off-load. It is based on a single perceptron hardware unit, enhanced with an additional accumulation input and scaling features, that is sequentially scheduled to cover all the nodes of the network. The accelerator supports both linear and Rectified Linear Unit (ReLU) activation and its firmware can be generated from 8-bit tflite quantized models. We also present a complete design toolchain that encompasses supervised learning, compilation, assembly, simulation, and device programming. The hardware support for extra accumulation input and scaling, together with the processor memory partitioning, are the key features that enable significant speedups. By solving a toy recognition problem based on image data captured from an infra-red camera, measurements show that the execution speed of SPLVP at 80 MHz outperforms an ARM Cortex-M4 STM32L476 microcontroller by a factor of 9.2 when the same ANN is translated to MCU code using the STM CubeMX-Ai converter at the same clock frequency. SPLVP is synthesized on a low-cost and gate-count Cyclone 10 LP FPGA resulting in an 18% logic and 77% memory occupation. The SPLVP assembly code can be directly converted into a VHDL description that directly hardcodes the ANN. The execution speed of an ANN model for Iris classification, fully synthesized, improves by a factor of 209 compared to firmware execution on the MCU. To verify the operation of SPLVP and its design framework, we have designed various tiny Machine Learning (ML) classifiers, for which we briefly discuss the obtained performance and the preprocessing techniques used. Across all these classifiers, the obtained speedup compared to the STM32 is 8.3-14.9 ×. INDEX TERMSNeural processing unit, multilayer perceptron, single perceptron linear vector processor, fully connected neural network, FPGA, compiler, design toolchain, MCU, tiny machine learning.

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“…Inference time comparison of SPLVP with respect to CNN-MLPA in [71] when synthesized for MLP operations, and for different number of PEs.…”

Section: Tablementioning

confidence: 99%

Section: Tablementioning

confidence: 99%