A SAR-based Fast Automatic Frequency Tuning Circuit in a 3-th Order Active-RC Complex Filter

Jin, Boyong; Chen, Zhijie; Liu, Xu; Shen, Zhiqi; Bao, Yucheng; Xing, Yanhui; Wan, Peiyuan

doi:10.1109/asid52932.2021.9651714

Cited by 1 publication

(2 citation statements)

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“…In this scheme, similar capacitors and resistors are employed in the filter to be tuned and the tuning module. Figure 2 shows the master circuit of a conventional auto-tuning method [ 15 , 18 ]. The circuit is composed of four parts: a current bias circuit, an integrator circuit, a comparator, and a digital block.…”

Section: Conventional Master–slave Tuning Schemementioning

confidence: 99%

“…In fact, high linearity is often very important in many cases [ 15 , 17 ]. The master–slave scheme is widely used to achieve auto-tuning of the RC time constant without interrupting the process of the system and preserve linearity [ 18 , 19 , 20 , 21 , 22 , 23 , 24 , 25 ]. In this scheme, similar capacitors and resistors are employed in the filter to be tuned and the tuning module.…”

Section: Introductionmentioning

confidence: 99%

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A High-Accuracy RC Time Constant Auto-Tuning Scheme for Integrated Continuous-Time Filters

Jin,

Wu,

Yin

et al. 2024

Micromachines

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The reliability of the resistor-capacitor (RC) time constant of a continuous-time (CT) filter has long been an obstacle with integrated circuits. Due to process and temperature variations in complementary metal-oxide semiconductor (CMOS) technology, the absolute value of the RC time constant may vary over ±50%, which is a big issue for many integrated continuous-time analog circuits. This study proposes an on-chip RC time constant auto-tuning scheme. The proposed scheme is based on the discrete master–slave auto-tuning concept. Considering the limitations in conventional works, a higher tuning accuracy is achieved by adopting two techniques: firstly, parasitic capacitance cancelation is proposed to eliminate the effects caused by parasitic capacitance; secondly, symmetric comparison is introduced to minimize the influence of the DC offset of the comparator. A successive approximation procedure is applied to improve the tuning speed. The proposed auto-tuning scheme has been validated in 55 nm CMOS technology with a fourth-order active-RC low-pass filter under PVT variations and 60 mV input offset voltage. The average tuning error is 2.21%, and the maximum error is 3.67%. The tuning error of the proposed scheme is considerably lower than the conventional scheme.

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Section: Conventional Master–slave Tuning Schemementioning

confidence: 99%