A SAW-less multiband WEDGE receiver

Gaborieau, Olivier; Mattisson, Sven; Klemmer, Nikolaus; Fahs, Bassem; Braz, Fabio T.; Gudmundsson, Richard; Mattsson, Thomas R.; Lascaux, C.; Trichereau, Christophe; Suter, W.; Westesson, Eric; Nydahl, Andreas

doi:10.1109/isscc.2009.4977334

Cited by 21 publications

(15 citation statements)

References 6 publications

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“…As described earlier out-of-band linearity poses a major challenge both in cellular FDD systems, like WCDMA/HSPA [1], [3] and CDMA [28], and in multistandard devices where several different radio protocols can operate simultaneously causing inter-system interference due to finite isolation between different RF nodes [7]. Therefore extensive research on different linearization techniques has resulted in remarkable improvements both with respect to IIP3 and IIP2 to enable the removal of bulky passive filters.…”

Section: A Receiver Architectures For Portable Devicesmentioning

confidence: 99%

“…Especially the trade-off between off-chip, passive out-of-band filtering and linearity remains a major challenge in highly optimized FDD (frequency-division duplexing) systems like WCDMA [1] or LTE. Local RF loops have been proposed to remove the highest blockers for example using feed-forward injection in [2] but still most of the commercial receivers, e.g., [3] techniques [4] including bandpass approach [5] have been presented as solutions for a software-defined radio (SDR) [6]. However, they can not address the RF linearity issue, and especially converters suffer from limited dynamic range and in many cases also from excessive power consumption.…”

Section: Introductionmentioning

confidence: 99%

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A 900-MHz Direct Delta-Sigma Receiver in 65-nm CMOS

Koli

Kallioinen

Jussila

et al. 2010

IEEE J. Solid-State Circuits

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Direct delta-sigma receiver architecture is introduced for wireless communication systems, such as LTE or WiMax. Architecture is based on direct downconversion, delta-sigma feedback that is up-converted to RF, and N-path filtering technique. Hence, the core receiver functions including channel selection filtering are embedded to a RF ADC with excellent linearity performance. This is achieved by transforming narrow-band filtering partially to RF injecting feedback into the input of the second amplifier stage, hence relieving requirements of the most critical subsequent stages. A 900-MHz direct delta-sigma receiver prototype occupies an active area of 1 2 mm 2 in 65-nm CMOS. The receiver for low-band cellular operations achieves NF of 2.3 and 6.2 dB in conventional and delta-sigma modes, respectively, and out-of-band IIP3 up to +4 dBm when the delta-sigma loop is active. The chip consumes 80 mW from a 1.2-V supply.

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Section: A Receiver Architectures For Portable Devicesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 900-MHz Direct Delta-Sigma Receiver in 65-nm CMOS

Koli

Kallioinen

Jussila

et al. 2010

IEEE J. Solid-State Circuits

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“…A 2*LO-LO topology is used to realize a 25% duty cycle [1], and has good performance for the RF front-end mixer [2]. In this paper we present a new switching topology for a quadrature sampling mixer(QSM) to realize the 25% duty cycle for application in a SAW-less GPS receiver.…”

Section: Introductionmentioning

confidence: 99%

“…Due to limited isolation between TX and GPS receiver, a SAW filter is normally deployed to reject TX leakage, which degrades sensitivity and NF. However a SAW-less system is highly desired to save area and cost.A 2*LO-LO topology is used to realize a 25% duty cycle [1], and has good performance for the RF front-end mixer [2]. In this paper we present a new switching topology for a quadrature sampling mixer(QSM) to realize the 25% duty cycle for application in a SAW-less GPS receiver.…”

mentioning

confidence: 99%

Quadrature sampling mixer topology for SAW-Less GPS receivers in 0.18µm CMOS

Ikeuchi

Saito

Nauta

2010

2010 Symposium on VLSI Circuits

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This paper describes a new switching topology of a sampling mixer for SAW-less GPS (L1 band) receivers. The GPS receiver with the new mixer achieved NF 2.5dB and good blocking performance. In an alternative implementation, the mixer is stacked under a Quadrature VCO to reuse supply current. As a result, the current consumption of the GPS receiver is 11mA from 1.8V supply while maintaining blocking performance and NF of 3.5dB. Test chips are fabricated in 0.18μm CMOS process. IntroductionGlobal positioning system (GPS) is one of the noticeable mobile applications and meanwhile GPS receivers are widely integrated in cellular phones. In a system like WCDMA, the transmitter (TX) and GPS receiver operate simultaneously. Due to limited isolation between TX and GPS receiver, a SAW filter is normally deployed to reject TX leakage, which degrades sensitivity and NF. However a SAW-less system is highly desired to save area and cost.A 2*LO-LO topology is used to realize a 25% duty cycle [1], and has good performance for the RF front-end mixer [2]. In this paper we present a new switching topology for a quadrature sampling mixer(QSM) to realize the 25% duty cycle for application in a SAW-less GPS receiver. A QSM can have a filter function besides down-conversion [3]. Hence it is an attractive solution for SAW-less systems. This paper describes two test chips, which are Type I and Type II. The details of them are mentioned in later section.The GPS signal coming from the satellite consists of two carriers, which are L1 band (1575.42MHz) and L2 band (1227.6MHz). We designed the RF front end of a L1 GPS receiver, which carries C/A code. The receiver uses a Low-IF of 4.092MHz, and the LO frequency is 1571.328MHz

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“…Minimization of the area occupied by the LNAs is therefore important. Virtually every transceiver for mobile phone applications published to date makes use of LNAs employing on-chip [3,5] or on-passivation [4] spiral inductors. Spiral inductors are large and do not scale with technology, leading to an increasing relative cost of the receiver front-end with newer technology nodes.…”

mentioning

confidence: 99%

A receiver for WCDMA/EDGE mobile phones with inductorless front-end in 65nm CMOS

Beffa¹,

Sin²,

Tanzil

et al. 2011

2011 IEEE International Solid-State Circuits Conference

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The spectrum allocated for the operation of cellular services is country dependent and fragmented in several frequency bands [1]. Mobile phones, to be usable globally, are therefore required to support many bands. The lack of suitable tuneable pre-selection filters and duplexers mandates the use of a large number of low-noise amplifiers (LNAs) in the receiver section of the transceiver. Minimization of the area occupied by the LNAs is therefore important. Virtually every transceiver for mobile phone applications published to date makes use of LNAs employing on-chip [3,5] or on-passivation [4] spiral inductors. Spiral inductors are large and do not scale with technology, leading to an increasing relative cost of the receiver front-end with newer technology nodes. Post-passivation and SiP technologies also add noticeably to the costs. In this paper we present the first receiver employing no on-chip or above-passivation spiral inductors on the receive signal path and with a linearity and noise performance suitable for WCDMA/EDGE applications. The eight channel direct-conversion receiver is part of a multimode transceiver requiring neither RX nor TX interstage SAW filters for FDD 3G operation. A block diagram of the receiver is shown in Fig. 21.4.1.The core of the receiver is constituted by the front-end, a simplified schematic of which is shown in Fig. 21.4.2. The variable-gain LNA is based on the shuntshunt feedback topology and provides a gain of 16, 7 or -5 dB. To break the otherwise fixed relation between input impedance and the transistor transconductance, a load impedance is used, consisting of two resistors connected in series with the core of a passive mixer. The impedance looking into the mixer RF port is made very low and the node is used as a virtual ground from DC up to GHz frequencies. The resistors R LIa , R LIb , R LQa and R LQb are not only used as load for the LNA, but they are also used (i) to transform the output voltage of the LNA into an input current for the passive mixer, (ii) to isolate the I channel from the Q channel and (iii) to improve the linearity of the mixer. The last point can be appreciated by noting that most of the mixer input voltage V o LNA is dropped across the load resistors and only a very small fraction of it is dropped across the switching transistors.To more easily explain the working of the pseudo-differential variable gain LNA, Fig. 21.4.3 shows the simplified schematic of one-half of a two-gain-settings version of the amplifier. To increase power efficiency, the transconductance is implemented as a complementary stage and comprises transistors M1, M5, M4 and M10. In high-gain mode the signal current from the transconductance stage is steered by the cascodes to the output node A of the amplifier. In this mode the feedback resistor consists of the series connection of R Fa and R Fb . The load resistors R LIa , R LQa leading to the mixer core are shown for illustration purpose connected to AC ground. In low-gain mode the signal current from the transconductance stage is st...

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A SAW-less multiband WEDGE receiver

Cited by 21 publications

References 6 publications

A 900-MHz Direct Delta-Sigma Receiver in 65-nm CMOS

A 900-MHz Direct Delta-Sigma Receiver in 65-nm CMOS

Quadrature sampling mixer topology for SAW-Less GPS receivers in 0.18µm CMOS

A receiver for WCDMA/EDGE mobile phones with inductorless front-end in 65nm CMOS

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A SAW-less multiband WEDGE receiver

Cited by 21 publications

References 6 publications

A 900-MHz Direct Delta-Sigma Receiver in 65-nm CMOS

A 900-MHz Direct Delta-Sigma Receiver in 65-nm CMOS

Quadrature sampling mixer topology for SAW-Less GPS receivers in 0.18&#x00B5;m CMOS

A receiver for WCDMA/EDGE mobile phones with inductorless front-end in 65nm CMOS

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Quadrature sampling mixer topology for SAW-Less GPS receivers in 0.18µm CMOS