1999
DOI: 10.1007/3-540-48059-5_10
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A Scalable Architecture for Montgomery Nultiplication

Abstract: Abstract. This paper describes the methodology and design of a scalable Montgomery multiplication module. There is no limitation on the maximum number of bits manipulated by the multiplier, and the selection of the word-size is made according to the available area and/or desired performance. We describe the general view of the new architecture, analyze hardware organization for its parallel computation, and discuss design tradeoffs which are useful to identify the best hardware configuration.

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Cited by 125 publications
(135 citation statements)
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“…Tenca and Koç [35] came up with a scalable pipelined design where the circuit of the Montgomery multiplier is split into "word size" processing elements. Since then, several improvements have been made to their original design [36,39].…”
Section: Related Workmentioning
confidence: 99%
“…Tenca and Koç [35] came up with a scalable pipelined design where the circuit of the Montgomery multiplier is split into "word size" processing elements. Since then, several improvements have been made to their original design [36,39].…”
Section: Related Workmentioning
confidence: 99%
“…Some have been integrating crypto-oriented instructions into the instruction set of General Purpose Processors (GPPs) [5,6,7]. Others had a more scalable approach as depicted in [8]. But none have had a systematic approach where hardware designers would look for a design which would be the 'best' trade-off between speed, security, chip area and power consumption.…”
Section: Having a Quantitative Approachmentioning
confidence: 99%
“…Figure 1 shows the Multiple-word High-Radix (2 k ) Montgomery Multiplication algorithm (MWR2 k MM), a generalization of the MM algorithm presented in [18]. A full-precision High-Radix Montgomery algorithm has been presented and proven to be correct in [8].…”
Section: High-radix Word-based Montgomery Algorithmmentioning
confidence: 99%
“…That is, the operands cannot exceed a fixed bit-size. Designs that can take operands with an arbitrary precision are researched in the ASIC [18] and the FPGA [2] realms.…”
Section: Introductionmentioning
confidence: 99%
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