A scalable configurable architecture for the massively parallel GCA model

Abstract

The global cellular automata model (GCA) is a massively parallel computation model which extends the classical cellular automata (CA) model with dynamic global neighbours. We present for that model a data parallel architecture which is scalable in the number of parallel pipelines and which uses application specific operators (adapted operators). The instruction set consists of control and RULE instructions. A RULE computes the next cell contents for each cell in the destination object. The machine consists of P pipelines. Each pipeline has an associated primary memory bank and has access to the global memory (real or emulated multiport memory). Therefore each pipeline can execute one cell operation in every clock cycle. The diffusion of particles was used as an example in order to demonstrate the adaptive operators, the machine programming and its performance. Particles which point to each other within a defined neighbourhood search space are interchanged. The pointers are modified in each generation by a pseudo random function. For that application, an application-specific data parallel machine with up to 32 pipelines was synthesised for an Altera field-programmable gate array. In addition, this application was described in the high-level language GCAL. The RULE instruction can also automatically be extracted from the GCAL program leading to the same generated application specific DPA machine.

Parallel implementation of aircraft disembarking and emergency evacuation based on cellular automata

“…Models based on CA lead to algorithms, which are fast when implemented on serial computers, because they exploit the inherent parallelism of the CA structure. These algorithms are also appropriate for implementation on massively parallel computers (Spezzano et al, 1996), such as the cellular automaton machine (CAM) (Wilding et al, 1991) or FPGAs (Jendrsczok et al, 2009;Georgoudas et al, 2010).…”

“…the total number of cells. There are recent CA-based applications that have been implemented in FPGA logic and display remarkable performance compared to the corresponding software (Murtaza et al, 2008;Jendrsczok et al, 2009;Kalogeropoulos et al, 2013;Progias and Sirakoulis, 2013). Furthermore, the motivation of FPGA utilization derives from the fact that this specific design could be a major part of an embedded electronic system.…”

Design and hardware implementation of unconventional computing systems for networks analysis and data center management

“…Moreover, the implementation of CA rules in VLSI circuits or FPGA logic will enhance their inherent parallel nature [40][41][42][43][44][45]. Consequently, CA can be considered as ideal computational models leading to algorithms which are fast when implemented on current multiprocessor computational systems as well on Graphic Processing Units (GPUs), because they exploit the inherent parallelism of the CA structure [46][47][48][49][50].…”

“…They are re-configurable, thus, enabling fault tolerance modeling. There are recent CA based applications that have been implemented in FPGA logic and display remarkable performance compared to the corresponding software [43][44][45][96][97][98][99].…”

“…Another advantage of CAs is the definition of the radius of the neighborhood and their ability to incorporate inhomogeneities; that makes the model able to cope with the increasing diversity of cache memory hierarchy on modern [111][112][113][114][115] and future processors. Nonetheless, CAs are known for their inherent parallel nature that is fully exploited when the CA rule is implemented on VLSI circuits or FPGA logic [40][41][42][43][44][45]. As a result, the hardware implementation of the CA based model can serve as a co-processor or a hardware accelerator, increasing the efficiency of a modern multicore system.…”