A scalable, fixed-shuffling, parallel FFT butterfly processing architecture for SDR environment

Abstract

This paper presents a programmable and high-efficient application specific instruction-set processor (ASIP) for fast Fourier transformation (FFT) processing based on software defined radio (SDR) methodology. It adopts single instruction multiple data (SIMD) architecture to exploit the parallelism of butterfly operations in FFT algorithm. The proposed ASIP features eight parallel radix-2 butterfly computations with fixed vector data shuffling pattern. In addition, a flexible vector address generation unit is proposed to support innerand inter-group addressing mode. Experiment results show that the proposed FFT ASIP is much more flexible than previous works and outperforms state-of-the-art FFT ASIP architectures in term of energyefficiency.

Online Generation of Constant Mulitplication Accelerators

“…Contemporary digital circuits that perform digital signal processing (DSP), error correction codes (ECC), fast fourier transformations (FFT) all implement this function [3], [6]. Specifically, FFT processing is one of the most critical components in the orthogonal frequency division multiplexing (OFDM) [4]. OFDM itself is used in technologies including WiMax, WAN and LTE just to mention a few.…”