A scalable H.264/AVC deblocking filter architecture

Cervero, T.; Otero, Andrés; López, Sebastián; Torre, Eduardo de la; Callicó, Gustavo M.; Riesgo, Teresa; Sarmiento, Roberto

doi:10.1007/s11554-013-0359-9

Cited by 2 publications

(4 citation statements)

References 32 publications

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“…A reconfigurable interface is composed of specific device routing nodes located at the border of the PE; if a neighbor module uses a compatible set of nodes in its interface, the communication between neighboring modules is enabled without requiring fixed interconnections. The authors in [34,45] used this approach to build a scalable systolic array for evolvable hardware and a scalable wavefront array to implement a deblocking filter. In both cases, the static system contains one RR that interfaces with the static system through specific nodes located at the border of the RR.…”

Section: Existing Approaches To Scalabilitymentioning

confidence: 99%

“…Fine-grain reconfiguration can also be used to enhance scalability. As explained before, the works presented in [34,45] surrounded the scalable architectures with communication and control modules that passed the input/output signals to the corresponding modules. This strategy can lead to considerable resource overhead for small overlays.…”

Section: A New Approach To Build a Scalable Bbnnmentioning

confidence: 99%

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A Dynamically Reconfigurable BbNN Architecture for Scalable Neuroevolution in Hardware

García¹,

Zamacola²,

Otero³

et al. 2020

Electronics

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In this paper, a novel hardware architecture for neuroevolution is presented, aiming to enable the continuous adaptation of systems working in dynamic environments, by including the training stage intrinsically in the computing edge. It is based on the block-based neural network model, integrated with an evolutionary algorithm that optimizes the weights and the topology of the network simultaneously. Differently to the state-of-the-art, the proposed implementation makes use of advanced dynamic and partial reconfiguration features to reconfigure the network during evolution and, if required, to adapt its size dynamically. This way, the number of logic resources occupied by the network can be adapted by the evolutionary algorithm to the complexity of the problem, the expected quality of the results, or other performance indicators. The proposed architecture, implemented in a Xilinx Zynq-7020 System-on-a-Chip (SoC) FPGA device, reduces the usage of DSPs and BRAMS while introducing a novel synchronization scheme that controls the latency of the circuit. The proposed neuroevolvable architecture has been integrated with the OpenAI toolkit to show how it can efficiently be applied to control problems, with a variable complexity and dynamic behavior. The versatility of the solution is assessed by also targeting classification problems.

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Section: Existing Approaches To Scalabilitymentioning

confidence: 99%

Section: A New Approach To Build a Scalable Bbnnmentioning

confidence: 99%

A Dynamically Reconfigurable BbNN Architecture for Scalable Neuroevolution in Hardware

García¹,

Zamacola²,

Otero³

et al. 2020

Electronics

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“…Most of the hybrid filtering architectures use two transpose buffers. Scalable deblocking filter architectures are implemented in [17] and [18]. Scalable architectures can support different video configurations by configuration setting or by reconfigurability to support the different demands of the consumer.…”

Section: Review Of Deblocking Filter Architecturesmentioning

confidence: 99%

“…If both ( 5) and ( 6) are satisfied and if ( 7) is not satisfied then only one pixel on both the sides of the edges is modified as in ( 21) and (22). If ( 5) is satisfied and if ( 6) is not satisfied, then the pixels p 0 , p 1 , p 2 and q 0 alone are modified as in ( 15) - (18). If ( 6) is satisfied and if ( 5) is not satisfied then the pixels q 0 , q 1 , q 2 and p 0 alone are modified as in ( 15), ( 18) - (20).…”

Section: ) Strong Filtermentioning

confidence: 99%

High-Throughput Deblocking Filter Architecture Using Quad Parallel Edge Filter for H.264 Video Coding Systems

Rajabai

Sivanantham

2019

IEEE Access

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With the increasing demand in electronic gadgets expecting better video quality for multimedia applications, various coding standards evolved for the past two decades and optimization on the architectures of the various modules used in the video codec is most popular. In this paper, an efficient architecture for deblocking filter used to smoothen the pixels of the decompressed video data is proposed, which utilizes both pipelining and parallelism. The filtering process follows a sequential order as filtering vertical edges of luma block and chroma block followed by the horizontal edges of the luma block and chroma block. Three pipeline stages are used and four edges, either vertical or horizontal are filtered in parallel. Internal buffers which hold the sub-blocks read from the external frame buffers are accessed in a ping pong fashion to filter the adjacent sub-edges and thus reducing the external memory access cycles. Due to parallelism with novel edge filtering order, self-transposing mechanism, and ping pong buffer access, the throughput is increased. The proposed quad parallel edge deblocking filter architecture is implemented using Synopsys 90 nm library. It achieves a target area of 19.8 K and can process a Macro Block in 58 clock cycles.

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A scalable H.264/AVC deblocking filter architecture

Cited by 2 publications

References 32 publications

A Dynamically Reconfigurable BbNN Architecture for Scalable Neuroevolution in Hardware

A Dynamically Reconfigurable BbNN Architecture for Scalable Neuroevolution in Hardware

High-Throughput Deblocking Filter Architecture Using Quad Parallel Edge Filter for H.264 Video Coding Systems

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