A scalable hybrid verification system based on HDL slicing

Banerjee, Somnath; Gupta, Tushar; Jain, Saurabh

doi:10.1109/hldvt.2011.6114164

Cited by 4 publications

(3 citation statements)

References 20 publications

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“…In our system, since only one or more component blocks are simulated and almost always individual blocks are of much smaller size than the original design, true scalability is achieved. Another drawback of the system described in [9] is the list of signals that can potentially have emulation mismatch needs to be specified by designer, since this list is used to pre-compute slices upfront. This is not a trivial task for modern day SoCs with hundreds of millions of signals.…”

Section: Previous Workmentioning

confidence: 99%

“…While this concept reduces value initialization overhead at the start of simulation, still the entire DUT needs to be loaded by the simulator, leaving the scalability problem unaddressed. An HDL slice based approach to achieve scalability in emulation/simulation based verification systems is presented in [9]. The entire DUT is run on emulator and once error is detected, one or more slices corresponding to the signals which triggered mismatch are transferred to HDL simulator for debug.…”

Section: Previous Workmentioning

confidence: 99%

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Fast and scalable hybrid functional verification and debug with dynamically reconfigurable co-simulation

Banerjee¹,

Gupta²

2012

Proceedings of the International Conference on Computer-Aided Design

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Hybrid functional verification and debug systems which combine high execution speed of logic emulators and full observability and controllability of software simulators are widely used, but suffer from scalability problem since software simulators cannot handle large and complex System-on-chip (SoC) designs efficiently, restricting their application to only relatively small designs. This paper presents a completely scalable hybrid verification and debug system based on dynamically reconfigurable co-simulation. Unlike existing systems, it allows one or more component logic blocks of a SoC to run on simulator for debugging while rest of the design still runs on emulator. The full design under test (DUT) is run on emulator at near hardware speed for long test sequences, and on error detection one or more logic blocks are transparently switched over to simulation for debugging, initializing the system as a piecewise cosimulator. Logic blocks can be flexibly relocated between simulator and emulator dynamically, without going through time consuming design recompilation phase, allowing designers to quickly debug functional issues. Application of the system to verification of real complex designs shows the effectiveness of our approach.

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Section: Previous Workmentioning

confidence: 99%

Section: Previous Workmentioning

confidence: 99%

Fast and scalable hybrid functional verification and debug with dynamically reconfigurable co-simulation

Banerjee¹,

Gupta²

2012

Proceedings of the International Conference on Computer-Aided Design

Self Cite

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show abstract

“…Especially for large-scale and complex SOC, the method of system-level function verification is a challenge. The method based on the software simulation and FPGA prototype verification cannot simultaneously satisfy the requirements of flexibility and the speed for large-scale design verification [4]. The verification object is a DSP which is used for digital signal processing and system control in this paper.…”

Section: Introductionmentioning

confidence: 99%

A System-Level SOC Verification Method based on Hardware Accelerator

Li¹,

Xie²,

Wang³

2013

IJEEE

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A system-level SOC verification method based on hardware accelerator is proposed in this paper. The storage mapping relationship is designed according to storage characteristics of the hardware accelerator, and the whole testbench is put into the accelerator directly, resulting in a quick migration to accelerator and an optimized memory area. In order to ensure the comprehensiveness, complexity and authenticity, the system feature description is extracted from different application scenarios, and the test cases are derived from the paths of data flow and control flow. Additionally, the system debugging is simplified by controlling the acceleration processing with the method of trigger-driver-based state transition diagram. By adopting the system-level verification method proposed in this paper, RTL design of a DSP chip is verified and the experiment results demonstrate an immense acceleration effect and a high accuracy in bug locating. Finally the DSP chip is implemented in 0.18um CMOS process and it works properly.  Index Terms-system-level SOC verification, hardware accelerator, storage mapping, trigger Shi-Jun Li received the B.S. degree in Electronic information engineering, Yunnan University, Yunnan, China. He is currently working toward the M.S. degree in integrated circuit and system at Peking University. He research interests include digital design and verification on SOC based on hardware accelerator.

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Enhanced tracing and visibility in logic emulation environment by optimized design slicing

Banerjee¹,

Gupta²

2012

2012 4th Asia Symposium on Quality Electronic Design (ASQED)

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A scalable hybrid verification system based on HDL slicing

Cited by 4 publications

References 20 publications

Fast and scalable hybrid functional verification and debug with dynamically reconfigurable co-simulation

Fast and scalable hybrid functional verification and debug with dynamically reconfigurable co-simulation

A System-Level SOC Verification Method based on Hardware Accelerator

Enhanced tracing and visibility in logic emulation environment by optimized design slicing

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