A scalable, low cost design-for-test architecture for UltraSPARC/spl trade/ chip multi-processors

Parulkar, Ishwar; Ziaja, T.; Pendurkar, R.; D’Souza, Allbright; Majumdar, Amitava

doi:10.1109/test.2002.1041825

Cited by 34 publications

(17 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…A diagnosis technique is not required in this model since each core has its own error-distinguishing technique which identifies the intermittent-error prone core. The duration of the core shutdown is either permanent [21], represented by an infinite loop between Boxes 7 and 8, or temporary [9] where a core enters the same loop for a short period of time.…”

Section: Recovery Scenariosmentioning

confidence: 99%

“…Traditionally, a processor that is diagnosed with a hardware error would be replaced with another hot or cold processor (hot/cold swapping) [9], [21]. Another recovery approach is to reconfigure the defective processor and facilitate "graceful degradation" where only the defective core or microarchitectural structure is shutdown [12], [22], [25]- [27].…”

Section: Experiments Setupmentioning

confidence: 99%

See 1 more Smart Citation

Intermittent Hardware Errors Recovery: Modeling and Evaluation

Rashid

Pattabiraman

Gopalakrishnan

2012

2012 Ninth International Conference on Quantitative Evaluation of Systems

View full text Add to dashboard Cite

Abstract-The frequency of hardware errors is increasing due to shrinking feature sizes, higher levels of integration, and increasing design complexity. Intermittent errors are those that occur non-deterministically at the same location. It has been shown that intermittent hardware errors contribute to about 39% of the total hardware failures. Intermittent faults have characteristics that are different than transient and permanent errors, which makes it challenging to devise efficient recovery techniques for them.In this paper, we evaluate the impact of different intermittent error recovery scenarios on the processor performance. To achieve this, we model a system that consists of a fault-tolerant multicore processor subject to intermittent faults. Our fault models are based on insights from related work at the physical level. We find that the frequency of the intermittent error and the relative importance of the error location play an important role in choosing the recovery action that maximizes the processor's performance.

show abstract

Section: Recovery Scenariosmentioning

confidence: 99%

Section: Experiments Setupmentioning

confidence: 99%

Intermittent Hardware Errors Recovery: Modeling and Evaluation

Rashid

Pattabiraman

Gopalakrishnan

2012

2012 Ninth International Conference on Quantitative Evaluation of Systems

View full text Add to dashboard Cite

show abstract

“…For example, while the Cell processor contains eight Synergistic Processing Elements (SPEs), Sony's PlayStation 3 video game console considers using only seven of them to increase the manufacturing yield [8]. This approach is also applied in Sun's UltraSPARC T1 processor [13], [14] and Azul's Vega2 chip [15].…”

Section: A Core-level Redundancy In Homogeneous Manycore Processorsmentioning

confidence: 99%

“…For example, one possible solution is to add a firmware layer below OS to record mapping information which is obtained after fabrication test. This is similar to the CORE AVAILABLE REG used in UltraSPARC T1 processor [13], [14]. OS and programmers always work on the reference topology while the firmware is responsible for transformation.…”

Section: Physical Topology and Virtual Topologymentioning

confidence: 99%

On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems

Zhang

Han

et al. 2009

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

Abstract-Homogeneous manycore systems are emerging for tera-scale computation and typically utilize Network-on-Chip (NoC) as the communication scheme between embedded cores. Effective defect tolerance techniques are essential to improve the yield of such complex integrated circuits. We propose to achieve fault tolerance by employing redundancy at the core-level instead of at the microarchitecture level. When faulty cores exist on-chip in this architecture, however, the physical topologies of various manufactured chips can be significantly different. How to reconfigure the system with the most effective NoC topology is a relevant research problem. In this paper, we first show that this problem is an instance of a well known NP-complete problem. We then present novel solutions for the above problem, which not only maximize the performance of the on-chip communication scheme, but also provide a unified topology to Operating System and application software running on the processor. Experimental results show the effectiveness of the proposed techniques.

show abstract

“…In order to ensure effective testing of an SOC based on megacores, the top-level TAM must communicate with lower-level TAMs within megacores. Moreover, the system-level test architecture must be able to reuse the existing test architecture within cores; redesign of core test structures must be kept to a minimum and it must be consistent with the design transfer model between the core designer and the core user [15].…”

Section: B Interactivementioning

confidence: 99%

Test planning for modular testing of hierarchical SOCs

Chakrabarty

Iyengar

Krasniewski

2005

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

Abstract-Multilevel test access mechanism (TAM) optimization is necessary for modular testing of hierarchical systems-on-chip (SOCs) that contain older-generation SOCs as embedded megacores. We consider the case where these older-generation SOCs are used as hard cores in new SOC designs, and they are delivered to the system integrator as optimized and technology-mapped layouts. We present three hierarchical test planning and TAM optimization flows that exploit recent advances in TAM design for flattened SOC hierarchies. These techniques are based on the reuse of existing TAM architectures within megacores and the optimization of the top-level TAM under the constraints imposed by "TAM-ed" megacores that are delivered either with or without a wrapper. We present a new megacore wrapper-design technique for the latter case. Unlike prior methods that assume flat test hierarchies, the proposed methods are directly applicable to real-world design-transfer models involving hard megacores between the core vendor and the system integrator for hierarchical SOCs. Experimental results are presented for four ITC'02 SOC test benchmarks that contain megacores.

show abstract

A scalable, low cost design-for-test architecture for UltraSPARC/spl trade/ chip multi-processors

Cited by 34 publications

References 8 publications

Intermittent Hardware Errors Recovery: Modeling and Evaluation

Intermittent Hardware Errors Recovery: Modeling and Evaluation

On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems

Test planning for modular testing of hierarchical SOCs

Contact Info

Product

Resources

About