A Scalable Network-on-Chip Microprocessor With 2.5D Integrated Memory and Accelerator

Manoj, P K; Lin, Jie; Zhu, Shasha; Yin, Yingying; Liu, Xu; Huang, Xiwei; Song, Changjian; Zhang, Wenqi; Yan, Mei; Yu, Zhou; Yu, Hao

doi:10.1109/tcsi.2016.2647322

Cited by 33 publications

(4 citation statements)

References 30 publications

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“…So, synthesizing the state-of-the-art CPR inference on embedded systems poses many challenges. Hardware is either constrained by the number of operations that can be executed in parallel or by the memory interface transmission rate [3].…”

Section: Motivation and Research Challengesmentioning

confidence: 99%

Weight Quantization Retraining for Sparse and Compressed Spatial Domain Correlation Filters

et al. 2021

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Using Spatial Domain Correlation Pattern Recognition (CPR) in Internet-of-Things (IoT)-based applications often faces constraints, like inadequate computational resources and limited memory. To reduce the computation workload of inference due to large spatial-domain CPR filters and convert filter weights into hardware-friendly data-types, this paper introduces the power-of-two (Po2) and dynamic-fixed-point (DFP) quantization techniques for weight compression and the sparsity induction in filters. Weight quantization re-training (WQR), the log-polar, and the inverse log-polar geometric transformations are introduced to reduce quantization error. WQR is a method of retraining the CPR filter, which is presented to recover the accuracy loss. It forces the given quantization scheme by adding the quantization error in the training sample and then re-quantizes the filter to the desired quantization levels which reduce quantization noise. Further, Particle Swarm Optimization (PSO) is used to fine-tune parameters during WQR. Both geometric transforms are applied as pre-processing steps. The Po2 quantization scheme showed better performance close to the performance of full precision, while the DFP quantization showed further closeness to the Receiver Operator Characteristic of full precision for the same bit-length. Overall, spatial-trained filters showed a better compression ratio for Po2 quantization after retraining of the CPR filter. The direct quantization approach achieved a compression ratio of 8 at 4.37× speedup with no accuracy degradation. In contrast, quantization with a log-polar transform is accomplished at a compression ratio of 4 at 1.12× speedup, but, in this case, 16% accuracy of degradation is noticed. Inverse log-polar transform showed a compression ratio of 16 at 8.90× speedup and 6% accuracy degradation. All the mentioned accuracies are reported for a common database.

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Section: Motivation and Research Challengesmentioning

confidence: 99%

Weight Quantization Retraining for Sparse and Compressed Spatial Domain Correlation Filters

et al. 2021

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“…2.5D integration, otherwise known as interposer technology, facilitates system-level integration of 2D/3D ICs in side-by-side fashion. That is, an interposer serves as integration carrier, accommodates some system-level interconnect fabric, and may even contain active components [147][148][149][150][151][152][153]. Building advanced electronic systems in the form of 2.5D ICs is considered less complex than 3D integration [147,150,153].…”

Section: D and 25d Integrationmentioning

confidence: 99%

Hardware Security For and Beyond CMOS Technology

Knechtel¹

2020

Proceedings of the 2020 International Symposium on Physical Design

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As with most aspects of electronic systems and integrated circuits, hardware security has traditionally evolved around the dominant CMOS technology. However, with the rise of various emerging technologies, whose main purpose is to overcome the fundamental limitations for scaling and power consumption of CMOS technology, unique opportunities arise also to advance the notion of hardware security. In this paper, I first provide an overview on hardware security in general. Next, I review selected emerging technologies, namely (i) spintronics, (ii) memristors, (iii) carbon nanotubes and related transistors, (iv) nanowires and related transistors, and (v) 3D and 2.5D integration. I then discuss their application to advance hardware security and also outline related challenges. CCS CONCEPTS• Security and privacy → Security in hardware; • Hardware → Emerging technologies.

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“…The CNN-based object detection requires a high volume of parameters and calculations to extract features in the image and make predictions about the objects [13][14][15]. To meet this requirement, many researchers adopt high-performance devices, such as graphics processing units (GPUs), central processing units (CPUs), field-programmable gate arrays (FPGAs), and application-specific integrated circuits (ASICs), to build onboard real-time systems [14,16].…”

Section: Introductionmentioning

confidence: 99%

FPGA Implementation for CNN-Based Optical Remote Sensing Object Detection

et al. 2021

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In recent years, convolutional neural network (CNN)-based methods have been widely used for optical remote sensing object detection and have shown excellent performance. Some aerospace systems, such as satellites or aircrafts, need to adopt these methods to observe objects on the ground. Due to the limited budget of the logical resources and power consumption in these systems, an embedded device is a good choice to implement the CNN-based methods. However, it is still a challenge to strike a balance between performance and power consumption. In this paper, we propose an efficient hardware-implementation method for optical remote sensing object detection. Firstly, we optimize the CNN-based model for hardware implementation, which establishes a foundation for efficiently mapping the network on a field-programmable gate array (FPGA). In addition, we propose a hardware architecture for the CNN-based remote sensing object detection model. In this architecture, a general processing engine (PE) is proposed to implement multiple types of convolutions in the network using the uniform module. An efficient data storage and access scheme is also proposed, and it achieves low-latency calculations and a high memory bandwidth utilization rate. Finally, we deployed the improved YOLOv2 network on a Xilinx ZYNQ xc7z035 FPGA to evaluate the performance of our design. The experimental results show that the performance of our implementation on an FPGA is only 0.18% lower than that on a graphics processing unit (GPU) in mean average precision (mAP). Under a 200 MHz working frequency, our design achieves a throughput of 111.5 giga-operations per second (GOP/s) with a 5.96 W on-chip power consumption. Comparison with the related works demonstrates that the proposed design has obvious advantages in terms of energy efficiency and that it is suitable for deployment on embedded devices.

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A Scalable Network-on-Chip Microprocessor With 2.5D Integrated Memory and Accelerator

Cited by 33 publications

References 30 publications

Weight Quantization Retraining for Sparse and Compressed Spatial Domain Correlation Filters

Weight Quantization Retraining for Sparse and Compressed Spatial Domain Correlation Filters

Hardware Security For and Beyond CMOS Technology

FPGA Implementation for CNN-Based Optical Remote Sensing Object Detection

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