A scalar architecture for pseudo vector processing based on slide-windowed registers

Abstract

In this paper, we present a new scalar architecture for high-speed vector processing. Without using cache memory, the proposed architecture tolerates main memory access latency by introducing slide-windowed floating-point registers with data preloading frmture and pipelined memory. The architecture can hold upward compatibility with existing scalar architectures.In the new architecture, software can control the window structure. This is the advantage compared with our previous work of registerwindows. Because of this advantage, registers are utilized more flexibly and computational efficiency is largely enhanced. Furthermore, this flexibility helps the compiler to generate efficient object codes easily.We have evaluated its performance on Livermore Fortran Kernels. The evaluation results show that the proposed architecture reduces the penalty of main memory access better than an ordinary scalar processor and a processor with cache prefetching. The proposed architectwe with 64 registers tolerates memory access latency of 30 CPU cycles. Compared with our previous work, the propmkd architecttie hides longer with fewer registers.

Status of the CP-PACS project

“…The e ciency decreases from 74% to 57% for a 64 4 lattice. The loss primarily comes from the bandwidth, which we hope to improve for the actual machine.…”

“…This can be carried out by an application of the software pipelining technique called module scheduling 5,4], which results in the scheduling shown in Fig. 2.…”

“…Allocation of x i and y i to local registers can be worked out by a coloring technique 6]; we refer to Ref. 4] for details .…”

“…4.1 are listed in Table 3. For quenched QCD we expect to carry out exhaustive measurements with the quark mass ranging from heavy to light for a lattice size of typically 64 4 . Simulations carried out for three values of lattice spacing to control the continuum limit should take about half a year of CPU time.…”

Computers for lattice field theories

“…However, this is not straightforward because the register fields for instructions are limited; the number of registers is usually limited to 32. To resolve this problem we introduce slide windows as well as preload and poststore instructions [17]. We also pipeline the memory.…”