A scaleable FIR filter using 32-bit floating-point complex arithmetic on a configurable computing machine

Walters, A.; Athanas, Peter

doi:10.1109/fpga.1998.707941

Cited by 5 publications

(3 citation statements)

References 3 publications

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“…For a given required accuracy, this result can be used to predict the expected size of a set of multiplication units. For example, a typical FIR filter [22] requires many multiplication units; the average size of a multiplication unit serves as a good basis for the prediction of the size of such a filter.…”

Section: Theoremmentioning

confidence: 99%

The use of configurable computing for computational kernels in scientific simulations

Jones

Nakad

Plassmann

et al. 2006

Future Generation Computer Systems

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Section: Theoremmentioning

confidence: 99%

The use of configurable computing for computational kernels in scientific simulations

Jones

Nakad

Plassmann

et al. 2006

Future Generation Computer Systems

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“…To avoid that compromise and to achieve less number of look-up tables, it is better to choose the proposed architecture which can directly perform arithmetic operations on the complex numbers that are represented using 16-bit subset of IEEE floating point format. Some works also tried to perform complex arithmetic using resource sharing and pipelining concepts, by using a single floating point adder and floating point multiplier for processing of both real and imaginary parts to implement a typical DSP benchmark like scalable FIR filter [4].…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of Complex Floating Point Processor Using FPGA

Pavuluri¹,

T.S.R²,

Rambabu³

2013

VLSICS

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“…Floating point FIR filters have been analyzed in detail [29], the Fast-Fourier-Transform has received particular attention [8,19], and Lienhart et al perform an N-body simulation [22] with custom floating point numbers. In our context vector and matrix operations are of particular interest.…”

Section: Floating Point Numbers On Fpgasmentioning

confidence: 99%

Pipelined Mixed Precision Algorithms on FPGAs for Fast and Accurate PDE Solvers from Low Precision Components

Strzodka¹,

Göddeke

2006

2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines

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FPGAs are becoming more and more attractive for high precision scientific computations. One of the main problems in efficient resource utilization is the quadratically growing resource usage of multipliers depending on the operand size. Many research efforts have been devoted to the optimization of individual arithmetic and linear algebra operations. In this paper we take a higher level approach and seek to reduce the intermediate computational precision on the algorithmic level by optimizing the accuracy towards the final result of an algorithm. In our case this is the accurate solution of partial differential equations (PDEs). Using the Poisson Problem as a typical PDE example we show that most intermediate operations can be computed with floats or even smaller formats and only very few operations (e.g. 1%) must be performed in double precision to obtain the same accuracy as a full double precision solver. Thus the FPGA can be configured with many parallel float rather than few resource hungry double operations. To achieve this, we adapt the general concept of mixed precision iterative refinement methods to FPGAs and develop a fully pipelined version of the Conjugate Gradient solver. We combine this solver with different iterative refinement schemes and precision combinations to obtain resource efficient mappings of the pipelined algorithm core onto the FPGA.

show abstract

A scaleable FIR filter using 32-bit floating-point complex arithmetic on a configurable computing machine

Cited by 5 publications

References 3 publications

The use of configurable computing for computational kernels in scientific simulations

The use of configurable computing for computational kernels in scientific simulations

Design and Implementation of Complex Floating Point Processor Using FPGA

Pipelined Mixed Precision Algorithms on FPGAs for Fast and Accurate PDE Solvers from Low Precision Components

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