A Scaling Compatible, Synthesis Friendly VCO-based Delta-sigma ADC Design and Synthesis Methodology

Xu, Biying; Li, Shaolan; Sun, Nan; Pan, David Z.

doi:10.1145/3061639.3062192

Cited by 25 publications

(8 citation statements)

References 19 publications

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“…As a result, the delay line based TDCs in [30] and [31] have reached up to 5GS/s using a single channel, which was previously only possible using Flash ADC or excessive paralleling (i.e., time interleaving), incurring significant area and power overhead. Along the same line, a design automation flow for a mostly digital voltage-controlled oscillator (VCO)based delta-sigma ADC has been proposed and demonstrated recently [32]. Custom library and flow were combined with the digital design flow and scaling benefits were shown by comparing different processes.…”

Section: Digital-like Ams Operationsmentioning

confidence: 99%

Analog/Mixed-Signal Circuit Synthesis Enabled by the Advancements of Circuit Architectures and Machine Learning Algorithms

Su¹,

Zhang²,

Hassanpourghadi³

et al. 2021

Preprint

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Analog mixed-signal (AMS) circuit architecture has evolved towards more digital friendly due to technology scaling and demand for higher flexibility/reconfigurability. Meanwhile, the design complexity and cost of AMS circuits has substantially increased due to the necessity of optimizing the circuit sizing, layout, and verification of a complex AMS circuit. On the other hand, machine learning (ML) algorithms have been under exponential growth over the past decade and actively exploited by the electronic design automation (EDA) community. This paper will identify the opportunities and challenges brought about by this trend and overview several emerging AMS design methodologies that are enabled by the recent evolution of AMS circuit architectures and machine learning algorithms. Specifically, we will focus on using neural-network-based surrogate models to expedite the circuit design parameter search and layout iterations. Lastly, we will demonstrate the rapid synthesis of several AMS circuit examples from specification to silicon prototype, with significantly reduced human intervention.

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Section: Digital-like Ams Operationsmentioning

confidence: 99%

Analog/Mixed-Signal Circuit Synthesis Enabled by the Advancements of Circuit Architectures and Machine Learning Algorithms

Su¹,

Zhang²,

Hassanpourghadi³

et al. 2021

Preprint

View full text Add to dashboard Cite

show abstract

“…Over the past decade, mostly digital architectures [7], [16], [13], [14] have been widely explored in AMS circuit and system design to maximally leverage the increasing digital signal processing capability in advanced technology nodes. With more digital or digital-like (time-domain) operations, circuits and systems become more flexible and more compatible with supply scaling, which continuously reduces the headroom of conventional AMS designs.…”

Section: Delta-sigma Dacmentioning

confidence: 99%

“…In addition, these mostly digital architectures are typically less sensitive to process, voltage, and temperature variations and favor well-developed digital design automation tools. Design automations for SAR ADC [7], VCO-based ADC [16], and pulse-width and delta-sigma modulation DACs [13] Figure 9: Transition error models for a voltage pulse counterpart of ADC but also a fundamental block that is widely used in many other AMS circuits, such as ADCs and phase-locked loops. Third, DAC is a continuous-time system in which all transient information will influence performance.…”

Section: Delta-sigma Dacmentioning

confidence: 99%

Cepa

Zhang

Liu

et al. 2020

Proceedings of the 39th International Conference on Computer-Aided Design

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“…In another work on a voltage-controlled oscillator-based (VCO-based) ADC [27], only standard cells were employed, but the circuit layout was done manually. By registering custom-designed cells to a physical library, automatic P&R flows for analog circuits were introduced [17], [19], [23], [24], [28]. Also, hybrid methods for successive-approximation-register (SAR) ADCs were proposed with SKILL language for capacitive digitalto-analog converter (CDAC) generation [29], [30].…”

Section: Introductionmentioning

confidence: 99%

An All-Standard-Cell-Based Synthesizable SAR ADC With Nonlinearity-Compensated RDAC

Ojima

et al. 2021

IEEE Trans. VLSI Syst.

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We propose an all-standard-cell-based synthesizable successive-approximation-register analog-to-digital converter (SAR ADC) which is automatically placed and routed (P&R) using a commercial digital implementation tool. For higher feasibility and wider input range, a differential architecture is proposed with an inverter-based resistive digital-to-analog converter (RDAC) and a four-input comparator. MOSFET gate capacitance is employed for the sampling capacitor. To mitigate its capacitance variation due to input voltage and the leakage between gate and diffusion, we leave the diffusion of the standard cell floating and only use the capacitance between gate and bulk. Two prototypes have been designed in 65-nm bulk CMOS. Prototype I has been fabricated and achieves 10 MS/s, 14.3 mW, and 28.1-dB SNDR in a 6-bit architecture. The performance is improved in Prototype II by proposing a lookup table (LUT)-compensating transistor-configurable inverter-based RDAC and an OR-AND-Inverter (OAI)-based comparator and by employing a thick-oxide diffusion-floating decoupling cell for the sampling capacitor. The default LUT is created during the design phase by a script-controlled automatic simulation routine. The power consumption is significantly reduced as well through improved timing control. Layout-parasitic-extraction (LPE) simulations of Prototype II suggest 35.7-and 47.2-dB SNDRs in 6-and 8-bit versions, respectively. The power consumptions are reduced to 0.91 and 2.52 mW, respectively.

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A Scaling Compatible, Synthesis Friendly VCO-based Delta-sigma ADC Design and Synthesis Methodology

Cited by 25 publications

References 19 publications

Analog/Mixed-Signal Circuit Synthesis Enabled by the Advancements of Circuit Architectures and Machine Learning Algorithms

Analog/Mixed-Signal Circuit Synthesis Enabled by the Advancements of Circuit Architectures and Machine Learning Algorithms

Cepa

An All-Standard-Cell-Based Synthesizable SAR ADC With Nonlinearity-Compensated RDAC

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