A scaling scenario of asymmetric coding to reduce both data retention and program disturbance of NAND flash memories

Doi, Masafumi; Tanakamaru, Shuhei; Takeuchi, Ken

doi:10.1016/j.sse.2013.12.004

Cited by 9 publications

(2 citation statements)

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“…However, for weakly correlated data, the complex polynomial fitting operations will bring extra power consumption and delay. The asymmetric coding (AC) scheme [7] intercepts a data segment to compare the ratios of 0s and 1s. If 0's ratio is higher than 1's, then flip the data segment and the flipping flag bit ''1'' is appended to the data segment.…”

Section: Related Work a Error Mitigation 1) Data Preprocessingmentioning

confidence: 99%

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CeSR + Assisted LDPC: A Holistic Strategy to Improve MLC NAND Flash Reliability

et al. 2020

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NAND flash suffers from program interference and retention errors, which negatively affect its reliability. Existing schemes preprocess raw data before writing them to reduce Raw Bit Error Rate (RBER) and leverage ECCs (such as LDPC codes) to reduce Uncorrectable Bit Error Rate (UBER). Prior arts failed to take into account the counteractions between the program interference and retention errors.Thus, they may lead to sub-optimal error avoidance. Besides, after the preprocessing procedure, data randomness may be affected. Since NAND flash shows numerical-correlated error characteristics, there's a potential to provide such information to LDPC codes to further improve performance. In this article, we propose a holistic strategy consisting of two coupled procedures to enhance flash reliability. First, we use our previously proposed CeSR strategy to reduce RBER. Second, we improve the existing LDPC codes and name it Assisted LDPC strategy to reduce UBER. The Assisted LDPC is deeply coupled with CeSR. It leverages the data pattern after CeSR to improve the decoding success rate and accelerate the decoding procedure. The evaluation shows that compared with the state-of-the-art NRC strategy, CeSR can reduce the RBER of hot and cold data by up to 20.30% and 85.13%, respectively. Besides, compared with the traditional LDPC, the Assisted LDPC decoding strategy can increase the decoding success rate by up to 97% for cold data and reduce the average decoding iteration number of MSB pages for hot and cold data by up to 31.6% and 73.9%, respectively. INDEX TERMS Cell state remapping, flash reliability, LDPC codes, NAND flash memory, program interference, retention error.

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Section: Related Work a Error Mitigation 1) Data Preprocessingmentioning

confidence: 99%

“…From the perspective of reducing RBER, our previous work [5] and existing works (DPA [6], AC [7] and NRC [8]) preprocess raw data before writing. Existing work [2] shows that both program interference and retention errors are numerical correlated.…”

Section: Introductionmentioning

confidence: 99%